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SN54LVT18502 Datasheet PDF

Part Number SN54LVT18502
Description 3.3-V ABT SCAN TEST DEVICE
Manufacture etcTI
Total Page 30 Pages
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Features: Datasheet pdf SN54LVT18502 3.3-V ABT SCAN TEST DEVICE WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS SCBS669 – JULY 1996 D Member of the Texas Instruments SCOPE ™ Family of T estability Products D Member of the Tex as Instruments Widebus ™ Family D Sta te-of-the-Art 3.3-V ABT Design Supports Mixed-Mode Signal Operation (5-V Input and Output Voltages With 3.3-V VCC) D Supports Unregulated Battery Operation Down to 2.7 V D UBT ™ (Universal Bus Transceiver) Combines D-Type Latches an d D-Type Flip-Flops for Operation in Tr ansparent, Latched, or Clocked Mode D B us Hold on Data Inputs Eliminates the N eed for External Pullup Resistors D Co mpatible With the IEEE Standard 1149.1- 1990 (JTAG) Test Access Port and Bounda ry-Scan Architecture D SCOPE ™ Instru ction Set – IEEE Standard 1149.1-1990 Required Instructions and Optional CLA MP and HIGHZ – Parallel-Signature Ana lysis at Inputs – Pseudo-Random Patte rn Generation From Outputs – Sample I nputs/Toggle Outputs – Binary Count From Outputs – Device Identification – Even-P.

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SN54LVT18502 Datasheet
SN54LVT18502
3.3-V ABT SCAN TEST DEVICE
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS669 – JULY 1996
D Member of the Texas Instruments SCOPE
Family of Testability Products
D Member of the Texas Instruments
Widebus Family
D State-of-the-Art 3.3-V ABT Design Supports
Mixed-Mode Signal Operation (5-V Input
and Output Voltages With 3.3-V VCC)
D Supports Unregulated Battery Operation
Down to 2.7 V
D UBT (Universal Bus Transceiver)
Combines D-Type Latches and D-Type
Flip-Flops for Operation in Transparent,
Latched, or Clocked Mode
D Bus Hold on Data Inputs Eliminates the
Need for External Pullup Resistors
D Compatible With the IEEE Standard
1149.1-1990 (JTAG) Test Access Port and
Boundary-Scan Architecture
D SCOPE Instruction Set
– IEEE Standard 1149.1-1990 Required
Instructions and Optional CLAMP and
HIGHZ
– Parallel-Signature Analysis at Inputs
– Pseudo-Random Pattern Generation
From Outputs
– Sample Inputs/Toggle Outputs
– Binary Count From Outputs
– Device Identification
– Even-Parity Opcodes
D Packaged in 68-Pin Ceramic Quad Flat (HV)
Packages Using 25-mil Center-to-Center
Spacings
HV PACKAGE
(TOP VIEW)
1A3
1A4
1A5
GND
1A6
1A7
1A8
1A9
NC
VCC
2A1
2A2
2A3
GND
2A4
2A5
2A6
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10 60
11 59
12 58
13 57
14 56
15 55
16 54
17 53
18 52
19 51
20 50
21 49
22 48
23 47
24 46
25 45
26 44
27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43
1B4
1B5
1B6
GND
1B7
1B8
1B9
VCC
NC
2B1
2B2
2B3
2B4
GND
2B5
2B6
2B7
NC – No internal connection
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
SCOPE, Widebus, and UBT are trademarks of Texas Instruments Incorporated.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Copyright © 1996, Texas Instruments Incorporated
On products compliant to MIL-PRF-38535, all parameters are tested
unless otherwise noted. On all other products, production
processing does not necessarily include testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
1

SN54LVT18502 Datasheet
SN54LVT18502
3.3-V ABT SCAN TEST DEVICE
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS669 – JULY 1996
description
The SN54LVT18502 scan test device with 18-bit universal bus transceivers is a member of the Texas
Instruments SCOPEtestability integrated-circuit family. This family of devices supports IEEE Standard
1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test
circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, this device is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability
to provide a TTL interface to a 5-V system environment.
In the normal mode, this device is an 18-bit universal bus transceiver that combines D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. It can be used either as two 9-bit
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples
of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP
in the normal mode does not affect the functional operation of the SCOPEuniversal bus transceivers.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level.
Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the
B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is
similar to A-to-B data flow, but uses the OEBA, LEBA, and CLKBA inputs.
In the test mode, the normal operation of the SCOPEuniversal bus transceivers is inhibited and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs
other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54LVT18502 is characterized for operation over the full military temperature range of –55°C to 125°C.
FUNCTION TABLE†
(normal mode, each register)
INPUTS
OUTPUT
OEAB LEAB CLKAB A
B
LL
L X B0‡
LL
L
L
LL
H
H
LH
XL
L
LH
XH
H
HX
XX
Z
A-to-B data flow is shown. B-to-A data flow is similar
but uses OEBA, LEBA, and CLKBA.
Output level before the indicated steady-state input
conditions were established
2 POST OFFICE BOX 655303 DALLAS, TEXAS 75265




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