3.3-V ABT SCAN TEST DEVICE
WITH 18-BIT UNIVERSAL BUS TRANSCEIVERS
SCBS669 – JULY 1996
The SN54LVT18502 scan test device with 18-bit universal bus transceivers is a member of the Texas
Instruments SCOPE™ testability integrated-circuit family. This family of devices supports IEEE Standard
1149.1-1990 boundary scan to facilitate testing of complex circuit-board assemblies. Scan access to the test
circuitry is accomplished via the 4-wire test access port (TAP) interface.
Additionally, this device is designed specifically for low-voltage (3.3-V) VCC operation, but with the capability
to provide a TTL interface to a 5-V system environment.
In the normal mode, this device is an 18-bit universal bus transceiver that combines D-type latches and D-type
flip-flops to allow data flow in transparent, latched, or clocked modes. It can be used either as two 9-bit
transceivers or one 18-bit transceiver. The test circuitry can be activated by the TAP to take snapshot samples
of the data appearing at the device pins or to perform a self test on the boundary-test cells. Activating the TAP
in the normal mode does not affect the functional operation of the SCOPE™ universal bus transceivers.
Data flow in each direction is controlled by output-enable (OEAB and OEBA), latch-enable (LEAB and LEBA),
and clock (CLKAB and CLKBA) inputs. For A-to-B data flow, the device operates in the transparent mode when
LEAB is high. When LEAB is low, the A-bus data is latched while CLKAB is held at a static low or high logic level.
Otherwise, if LEAB is low, A-bus data is stored on a low-to-high transition of CLKAB. When OEAB is low, the
B outputs are active. When OEAB is high, the B outputs are in the high-impedance state. B-to-A data flow is
similar to A-to-B data flow, but uses the OEBA, LEBA, and CLKBA inputs.
In the test mode, the normal operation of the SCOPE™ universal bus transceivers is inhibited and the test
circuitry is enabled to observe and control the I/O boundary of the device. When enabled, the test circuitry
performs boundary-scan test operations according to the protocol described in IEEE Standard 1149.1-1990.
Four dedicated test pins are used to observe and control the operation of the test circuitry: test data input (TDI),
test data output (TDO), test mode select (TMS), and test clock (TCK). Additionally, the test circuitry performs
other testing functions such as parallel-signature analysis (PSA) on data inputs and pseudo-random pattern
generation (PRPG) from data outputs. All testing and scan operations are synchronized to the TAP interface.
Active bus-hold circuitry is provided to hold unused or floating data inputs at a valid logic level.
The SN54LVT18502 is characterized for operation over the full military temperature range of –55°C to 125°C.
(normal mode, each register)
OEAB LEAB CLKAB A
L X B0‡
† A-to-B data flow is shown. B-to-A data flow is similar
but uses OEBA, LEBA, and CLKBA.
‡ Output level before the indicated steady-state input
conditions were established
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