SN65556 Datasheet | etcTI





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SN65556 Datasheet PDF

Part Number SN65556
Description Electroluminescent Column Drivers
Manufacture etcTI
Total Page 9 Pages
PDF Download Download SN65556 Datasheet

Features: Datasheet pdf Each Device Drives 32 Electrodes 90-V Ou tput Voltage Swing Capability Using Ram ped Supply 15-mA Output Source and Sink Current Capability High-Speed Serially -Shifted Data Input Totem-Pole Outputs Latches on All Driver Outputs descripti on The SN65555, SN75555, SN65556, and S N75556 are monolithic BIDFET† integra ted circuits designed to drive the colu mn electrodes of an electroluminescent display. The SN65556 and SN75556 output sequence is reversed from the SN65555 and SN75555 for ease in printed-circuit board layout. The devices consist of a 32-bit shift register, 32 latches, and 32 output AND gates. Serial data is ent ered into the shift register on the low -to-high transition of CLOCK. When high , LATCH ENABLE transfers the shift regi ster contents to the outputs of the 32 latches. When OUTPUT ENABLE is high, al l Q outputs are enabled. Data must be l oaded into the latches and OUTPUT ENABL E must be high before supply voltage VC C2 is ramped up. Serial data output from the shift register can b.

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SN65556 Datasheet
Each Device Drives 32 Electrodes
90-V Output Voltage Swing Capability
Using Ramped Supply
15-mA Output Source and Sink Current
Capability
High-Speed Serially-Shifted Data Input
Totem-Pole Outputs
Latches on All Driver Outputs
description
The SN65555, SN75555, SN65556, and
SN75556 are monolithic BIDFETintegrated
circuits designed to drive the column electrodes of
an electroluminescent display. The SN65556 and
SN75556 output sequence is reversed from the
SN65555 and SN75555 for ease in printed-circuit-
board layout.
The devices consist of a 32-bit shift register, 32
latches, and 32 output AND gates. Serial data is
entered into the shift register on the low-to-high
transition of CLOCK. When high, LATCH ENABLE
transfers the shift register contents to the outputs
of the 32 latches. When OUTPUT ENABLE is
high, all Q outputs are enabled. Data must be
loaded into the latches and OUTPUT ENABLE
must be high before supply voltage VCC2 is
ramped up.
Serial data output from the shift register can be
used to cascade shift registers. This output is not
affected by LATCH ENABLE or OUTPUT
ENABLE.
The SN65555 and SN65556 are characterized for
operation from 40 C to 85 C. The SN75555 and
SN75556 are characterized for operation from
0 C to 70 C.
SLDS031A APRIL 1985 REVISED APRIL 1993
SN75555 . . . N PACKAGE
(TOP VIEW)
Q17
Q16
Q15
Q14
Q13
Q12
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
SERIAL OUT
CLOCK
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 Q18
39 Q19
38 Q20
37 Q21
36 Q22
35 Q23
34 Q24
33 Q25
32 Q26
31 Q27
30 Q28
29 Q29
28 Q30
27 Q31
26 Q32
25 OUTPUT ENABLE
24 DATA IN
23 LATCH ENABLE
22 VCC1
21 VCC2
SN65555, SN75555 . . . FN PACKAGE
(TOP VIEW)
Q11
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
Q23
Q24
Q25
Q26
Q27
Q28
Q29
Q30
Q31
Q32
NC
NC No internal connection
BIDFET Bipolar, double-diffused, N-channel and P-channel MOS transistors on same chip. This is a patented process.
Copyright 1993, Texas Instruments Incorporated
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
41

SN65556 Datasheet
SLDS031A APRIL 1985 REVISED APRIL 1993
SN65556, SN75556
N PACKAGE
(TOP VIEW)
Q16
Q17
Q18
Q19
Q20
Q21
Q22
Q23
Q24
Q25
Q26
Q27
Q28
Q29
Q30
Q31
Q32
SERIAL OUT
CLOCK
GND
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
40 Q15
39 Q14
38 Q13
37 Q12
36 Q11
35 Q10
34 Q9
33 Q8
32 Q7
31 Q6
30 Q5
29 Q4
28 Q3
27 Q2
26 Q1
25 OUTPUT ENABLE
24 DATA IN
23 LATCH ENABLE
22 VCC1
21 VCC2
SN65556, SN75556
FN PACKAGE
(TOP VIEW)
Q22
Q23
Q24
Q25
Q26
Q27
Q28
Q29
Q30
Q31
Q32
6 5 4 3 2 1 44 43 42 41 40
7 39
8 38
9 37
10 36
11 35
12 34
13 33
14 32
15 31
16 30
17 29
18 19 20 21 22 23 24 25 26 27 28
Q10
Q9
Q8
Q7
Q6
Q5
Q4
Q3
Q2
Q1
NC
NC No internal connection
logic symbols
VCC2 21
OUTPUT ENABLE 25
LATCH ENABLE 23
CLOCK 19
DATA IN 24
SN65555, SN75555
CMOS/EL DISP
[PWR Q1-32]
EN3
C2
SRG 32
C1/
1D 2D 3
2D 3
VCC2 21
OUTPUT ENABLE 25
LATCH ENABLE 23
17
16
Q1
Q2
CLOCK 19
DATA IN 24
SN65556, SN75556
CMOS/EL DISP
[PWR Q1-32]
EN3
C2
SRG 32
C1/
1D 2D 3
2D 3
26 Q1
27 Q2
2D
2D
3
3
1 Q17
40 Q18
2D 3 40 Q15
2D 3 1 Q16
2D
2D
3
3
27 Q31
26 Q32
18 SERIAL OUT
These symbols are in accordance with ANSI/IEEE Std 91-1984 and IEC Publication 617-12.
Pin numbers shown are for N packages.
2D
2D
3
3
16
17
18
Q31
Q32
SERIAL OUT
42
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




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