SN74ABT126

D Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C D High-Impedance State During Power Up and Power Down D High-Drive Outputs (−32-mA IOH, 64-mA IOL) SN54ABT126, SN74ABT126 QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS SCBS183H − FEBRUARY 1991 − REVISED MAY 2003 D Ioff and Power-Up 3-State Support Hot Insertion D Latch-Up Performance Exceeds 500 mA Per JESD 17 D ESD Protection Exceeds JESD 22 − 2000-V Human-Body Model (A114-A) − 200-V Machine Model (A115-A) SN54ABT126 . . . J PACKAGE SN74ABT126 . . . D, DB, N, NS, OR PW PACKAGE (TOP VIEW) 1OE 1 1A 2 1Y 3 2OE 4 2A 5 2Y 6 GND 7 14 VCC 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 3Y SN74ABT126 . . . RGY PACKAGE (TOP VIEW) 1OE VCC 1 1A 2 1Y 3 2OE 4 2A 5 2Y 6 7 14 13 4OE 12 4A 11 4Y 10 3OE 9 3A 8 SN54ABT126 . . . FK PACKAGE (TOP VIEW) 1A 1OE NC VCC 4OE 1Y NC 2OE NC 2A 3 2 1 20 19 4 18 5 17 6 16 7 15 8 14 9 10 11 12 13 4A NC 4Y NC 3OE 2Y GND NC 3Y 3A GND 3Y description/ordering information NC − No internal connection The ’ABT126 bus buffer gates feature independent line drivers with 3-state outputs. Each output is disabled when the associated output-enable (OE) input is low. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be tied to GND through a pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver. ORDERING INF...