SN74ABT240A

D Typical VOLP (Output Ground Bounce) <1 V at VCC = 5 V, TA = 25°C D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Ioff Supports Partial-Power-Down Mode Operation D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) description These octal buffers and line drivers are designed specifically to improve both the performance and density of 3-state memory address drivers, clock drivers, and bus-oriented receivers and transmitters. Together with the SN54ABT241, SN74ABT241A, SN54ABT244, and SN74ABT244A, these devices provide the choice of selected combinations of inverting and noninverting outputs, symmetrical active-low output-enable (OE) inputs, and complementary OE and OE inputs. The SN54ABT240 and SN74ABT240A are organized as two 4-bit buffers/line drivers with separate OE inputs. When OE is low, the devices pass inverted data from the A inputs to the Y outputs. When OE is high, the outputs are in the high-impedance state. 2Y1 GND 2A1 1Y4 2A2 SN54ABT240, SN74ABT240A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS098I – JANUARY 1991 – REVISED JUNE 2002 SN54ABT240 . . . J OR W PACKAGE SN74ABT240A . . . DB, DW, N, NS, OR PW PACKAGE (TOP VIEW) 1OE 1A1 2Y4 1A2 2Y3 1A3 2Y2 1A4 2Y1 GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 2OE 18 1Y1 17 2A4 16 1Y2 15 2A3 14 1Y3 13 2A2 12 1Y4 11 2A1 SN54ABT240 . . . FK PACKAGE (TOP VIEW) 2Y4 1A1 1OE VCC 2OE 1A2 3 2 1 20 19 4 18 ...