SN74ABT3612

SN74ABT3612 64 × 36 × 2 CLOCKED BIDIRECTIONAL FIRST-IN, FIRST-OUT MEMORY SCBS129G – JULY 1992 – REVISED APRIL 1998 D Free-Running CLKA and CLKB Can Be Asynchronous or Coincident D Two Independent 64 × 36 Clocked FIFOs Buffering Data in Opposite Directions D Mailbox-Bypass Register for Each FIFO D Programmable Almost-Full and Almost-Empty Flags D Microprocessor Interface Control Logic D EFA, FFA, AEA, and AFA Flags Synchronized by CLKA D EFB, FFB, AEB, and AFB Flags Synchronized by CLKB D Passive Parity Checking on Each Port D Parity Generation Can Be Selected for Each Port D Low-Power Advanced BiCMOS Technology D Supports Clock Frequencies up to 67 MHz D Fast Access Times of 10 ns D Package Options Include 120-Pin Thin Quad Flat (PCB) and 132-Pin Plastic Quad Flat (PQ) Packages description The SN74ABT3612 is a high-speed, low-power BiCMOS bidirectional clocked FIFO memory. It supports clock frequencies up to 67 MHz and has read access times as fast as 10 ns. Two independent 64 × 36 dual-port SRAM FIFOs in this device buffer data in opposite directions. Each FIFO has flags to indicate empty and full conditions and two programmable flags (almost-full and almost-empty) to indicate when a selected number of words is stored in memory. Communication between each port can bypass the FIFOs via two 36-bit mailbox registers. Each mailbox register has a flag to signal when new mail has been stored. Parity is checked passively on each port and can be ignored if not desired. Parity gen...