DatasheetsPDF.com

SN74ABT827 Datasheet

Part Number SN74ABT827
Manufacturers Texas Instruments
Logo Texas Instruments
Description 10-Bit Buffer/Drivers
Datasheet SN74ABT827 DatasheetSN74ABT827 Datasheet (PDF)

SN54ABT827, SN74ABT827 10ĆBIT BUFFERS/DRIVERS WITH 3ĆSTATE OUTPUTS SCBS159E − JANUARY 1991 − REVISED APRIL 2005 D State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation D Flow-Through Architecture Optimizes PCB Layout D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D High-Impedance State During Power Up and Power Down D High-Drive Outputs (−32-mA IOH, 64-mA IOL) D Package Options Inclu.

  SN74ABT827   SN74ABT827






Part Number SN74ABT8245
Manufacturers Texas Instruments
Logo Texas Instruments
Description SCAN TEST DEVICES
Datasheet SN74ABT827 DatasheetSN74ABT8245 Datasheet (PDF)

SN54ABT8245, SN74ABT8245 SCAN TEST DEVICES WITH OCTAL BUS TRANSCEIVERS SCBS124D – AUGUST 1992 – REVISED DECEMBER 1996 D Members of the Texas Instruments SCOPE ™ Family of Testability Products D Compatible With the IEEE Standard 1149.1-1990 (JTAG) Test Access Port and Boundary-Scan Architecture D Functionally Equivalent to ’F245 and ’ABT245 in the Normal-Function Mode D SCOPE ™ Instruction Set: – IEEE Standard 1149.1-1990 Required Instructions, Optional INTEST, CLAMP, and HIGHZ – Parallel-Signat.

  SN74ABT827   SN74ABT827







Part Number SN74ABT823
Manufacturers Texas Instruments
Logo Texas Instruments
Description 9-BIT BUS-INTERFACE FLIP-FLOPS
Datasheet SN74ABT827 DatasheetSN74ABT823 Datasheet (PDF)

SN54ABT823, SN74ABT823 9-BIT BUS-INTERFACE FLIP-FLOPS WITH 3-STATE OUTPUTS SCBS158E – JANUARY 1991 – REVISED MAY 1997 D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015; Exceeds 200 V Using Machine Model (C = 200 pF, R = 0) D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D High-Impedance State During Power Up and Power .

  SN74ABT827   SN74ABT827







Part Number SN74ABT821A
Manufacturers Texas Instruments
Logo Texas Instruments
Description 10-BIT BUS-INTERFACE FLIP-FLOPS
Datasheet SN74ABT827 DatasheetSN74ABT821A Datasheet (PDF)

D State-of-the-Art EPIC-ΙΙB™ BiCMOS Design Significantly Reduces Power Dissipation D ESD Protection Exceeds 2000 V Per MIL-STD-883, Method 3015 D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D High-Impedance State During Power Up and Power Down D High-Drive Outputs (–32-mA IOH, 64-mA IOL) D Package Options Include Plastic Small-Outline (DW) and Shrink Small-Outline (DB) Packages, Ceramic Chip Carriers (FK), Cer.

  SN74ABT827   SN74ABT827







10-Bit Buffer/Drivers

SN54ABT827, SN74ABT827 10ĆBIT BUFFERS/DRIVERS WITH 3ĆSTATE OUTPUTS SCBS159E − JANUARY 1991 − REVISED APRIL 2005 D State-of-the-Art EPIC-ΙΙB BiCMOS Design Significantly Reduces Power Dissipation D Flow-Through Architecture Optimizes PCB Layout D Latch-Up Performance Exceeds 500 mA Per JEDEC Standard JESD-17 D Typical VOLP (Output Ground Bounce) < 1 V at VCC = 5 V, TA = 25°C D High-Impedance State During Power Up and Power Down D High-Drive Outputs (−32-mA IOH, 64-mA IOL) D Package Options Include Plastic Small-Outline (DW), Shrink Small-Outline (DB), and Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK), and Plastic (NT) and Ceramic (JT) DIPs description SN54ABT827 . . . JT PACKAGE SN74ABT827 . . . DB, DW, NT, OR PW PACKAGE (TOP VIEW) OE1 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 A9 10 A10 11 GND 12 24 VCC 23 Y1 22 Y2 21 Y3 20 Y4 19 Y5 18 Y6 17 Y7 16 Y8 15 Y9 14 Y10 13 OE2 SN54ABT827 . . . FK PACKAGE (TOP VIEW) A2 A1 OE1 NC VCC Y1 Y2 These 10-bit buffers or bus drivers provide a high-performance bus interface for wide data paths or buses carrying parity. The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all ten outputs are in the high-impedance state. The ’ABT827 provides true data at the outputs. When VCC is between 0 and 2.1 V, the device is in the high-impedance state during power up or power down. However, to ensure the high-impedance state above 2.1 V, OE should be t.


2023-05-20 : SN54ABTH32543    SN54ABTH32318    SN54ABTH32316    54125    54126    54164    74164    54LS164    74LS164    LPC5504JHI48   


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)