SN74AHCT573-Q1 Datasheet


Part Number

SN74AHCT573-Q1

Description

Octal Transparent D-Type Latches

Manufacture

etcTI

Total Page 8 Pages
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Download SN74AHCT573-Q1 Datasheet


Features Datasheet pdf D Qualified for Automotive Applications D ESD Protection Exceeds 1500 V Per MIL -STD-883, Method 3015; Exceeds 150 V Us ing Machine Model (C = 200 pF, R = 0) D Inputs Are TTL-Voltage Compatible D La tch-Up Performance Exceeds 250 mA Per J ESD 17 SN74AHCT573ĆQ1 OCTAL TRANSPARE NT DĆTYPE LATCH WITH 3ĆSTATE OUTPUTS SCLS541A − SEPTEMBER 2003 − REVISED APRIL 2008 DW PACKAGE (TOP VIEW) OE 1 D 2D 3D 4D 5D 6D 7D 8D GND 1 2 3 4 5 6 7 8 9 10 20 VCC 19 1Q 18 2Q 17 3Q 16 4Q 15 5Q 14 6Q 13 7Q 12 8Q 11 LE descr iption/ordering information The SN74AHC T573 is an octal transparent D-type lat ch. When the latch-enable (LE) input is high, the Q outputs follow the data (D ) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs. A buffered output-enable (OE ) input can be used to place the eight outputs in either a normal logic state (high or low) or the high-impedance sta te. In the high-impedance state, the ou tputs neither load nor drive the bus lines significantly. The high-imp.
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SN74AHCT573-Q1 Datasheet
D Qualified for Automotive Applications
D ESD Protection Exceeds 1500 V Per
MIL-STD-883, Method 3015; Exceeds 150 V
Using Machine Model (C = 200 pF, R = 0)
D Inputs Are TTL-Voltage Compatible
D Latch-Up Performance Exceeds 250 mA Per
JESD 17
SN74AHCT573ĆQ1
OCTAL TRANSPARENT DĆTYPE LATCH
WITH 3ĆSTATE OUTPUTS
SCLS541A − SEPTEMBER 2003 − REVISED APRIL 2008
DW PACKAGE
(TOP VIEW)
OE
1D
2D
3D
4D
5D
6D
7D
8D
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 1Q
18 2Q
17 3Q
16 4Q
15 5Q
14 6Q
13 7Q
12 8Q
11 LE
description/ordering information
The SN74AHCT573 is an octal transparent D-type latch. When the latch-enable (LE) input is high, the Q outputs
follow the data (D) inputs. When LE is low, the Q outputs are latched at the logic levels of the D inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high
or low) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines
significantly. The high-impedance state and increased drive provide the capability to drive bus lines without
interface or pullup components.
To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup
resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver.
OE does not affect the internal operations of the latches. Old data can be retained or new data can be entered
while the outputs are in the high-impedance state.
ORDERING INFORMATION{
TA
PACKAGE‡
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
−40°C to 125°C SOIC − DW
Tape and reel SN74AHCT573QDWRQ1 AHCT573QQ1
For the most current package and ordering information, see the Package Option Addendum at the end of
this document, or see the TI web site at http://www.ti.com.
Package drawings, thermal data, and symbolization are available at http://www.ti.com/packaging.
FUNCTION TABLE
(each latch)
INPUTS
OE LE
D
OUTPUT
Q
L HH
H
LHL
L
LLX
HXX
Q0
Z
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright 2008, Texas Instruments Incorporated
1




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