SN74AUC1G74

www.ti.com SN74AUC1G74 SINGLE POSITIVE-EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH CLEAR AND PRESET SCES537D – DECEMBER 2003 – REVISED JUNE 2007 FEATURES Available in the Texas Instruments NanoFree™ Package Optimized for 1.8-V Operation and Is 3.6-V I/O Tolerant to Support Mixed-Mode Signal Operation Ioff Supports Partial-Power-Down Mode Operation Sub-1-V Operable Max tpd of 1.5 ns at 1.8 V DCT PACKAGE (TOP VIEW) DCU PACKAGE (TOP VIEW) Low Power Consumption, 10-μA Max ICC ±8-mA Output Drive at 1.8 V Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) RSE PACKAGE (TOP VIEW) YZP OR YZT PACKAGE (BOTTOM VIEW) 7 CLK 6D 5Q CLK 1 D 2 Q 3 GND 4 8 VCC CLK 1 D2 7 PRE Q3 6 CLR GND 4 5 Q 8 VCC 7 PRE 6 CLR 5Q VCC 8 4 GND GND 4 5 Q Q 3 6 CLR D 2 7 PRE CLK 1 8 VCC PRE 1 CLR 2 Q3 See mechanical drawings for dimensions. DESCRIPTION/ORDERING INFORMATION This single positive-edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation. A low level at the preset (PRE) or clear (CLR) input sets or resets the outputs, regardless of the levels of the other inputs. When PRE and CLR are inactive (high), data at the data (D) input meeting the setup time requirements is transferred to the outputs on the positive-going edge of the clock pul...