32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
D Member of the Texas Instruments
Widebus+ Family
D Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support ...
Description
D Member of the Texas Instruments
Widebus+ Family
D Optimized for 1.8-V Operation and is 3.6-V
I/O Tolerant to Support Mixed-Mode Signal
Operation
D Ioff Supports Partial-Power-Down Mode
Operation
D Sub 1-V Operable D Max tpd of 2.8 ns at 1.8 V D Low Power Consumption, 40-µA Max ICC
SN74AUCH32374 32-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
WITH 3-STATE OUTPUTS
SCES476 – AUGUST 2003
D ±8-mA Output Drive at 1.8 V D Bus Hold on Data Inputs Eliminates the
Need for External Pullup/Pulldown
Resistors
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
description/ordering information
This 32-bit edge-triggered D-type flip-flop is operational at 0.8-V to 2.7-V VCC, but is designed specifically for 1.65-V to 1.95-V VCC operation.
The SN74AUCH32374 is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. It can be used as four 8-bit flip-flops, two 16-bit flip-flops, or one 32-bit flip-flop. On the positive transition of the clock (CLK) input, the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.
A buffered output-enable (OE) input can be used to place the eight outputs in either a normal logic state (high or low logic levels) or the high-impedance state. In the high-impedance state, the outputs neither load nor drive the bus lines significantly. Th...
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