SN74BCT541AN

D Operating Voltage Range of 4.5 V to 5.5 V D State-of-the-Art BiCMOS Design Significantly Reduces ICCZ D 3-State Outputs Drive Bus Lines or Buffer Memory Address Registers SN54BCT541 . . . J OR W PACKAGE SN74BCT541A . . . DW, N, OR NS PACKAGE (TOP VIEW) SN54BCT541, SN74BCT541A OCTAL BUFFERS/DRIVERS WITH 3-STATE OUTPUTS SCBS011E – JULY 1988 – REVISED MARCH 2003 D P-N-P Inputs Reduce DC Loading D Data Flow-Through Pinout (All Inputs on Opposite Side From Outputs) SN54BCT541 . . . FK PACKAGE (TOP VIEW) A2 A1 OE1 VCC OE2 OE1 1 A1 2 A2 3 A3 4 A4 5 A5 6 A6 7 A7 8 A8 9 GND 10 20 VCC 19 OE2 18 Y1 17 Y2 16 Y3 15 Y4 14 Y5 13 Y6 12 Y7 11 Y8 A8 GND Y8 Y7 Y6 A3 3 2 1 20 19 4 18 Y1 A4 5 17 Y2 A5 6 16 Y3 A6 7 15 Y4 A7 8 14 Y5 9 10 11 12 13 description/ordering information The SN54BCT541 and SN74BCT541A octal buffers and line drivers are ideal for driving bus lines or buffering memory-address registers. The devices feature inputs and outputs on opposite sides of the package to facilitate printed-circuit-board layout. The 3-state control gate is a 2-input AND gate with active-low inputs so that, if either output-enable (OE1 or OE2) input is high, all eight outputs are in the high-impedance state. To ensure the high-impedance state during power up or power down, OE should be tied to VCC through a pullup resistor; the minimum value of the resistor is determined by the current-sinking capability of the driver. ORDERING INFORMATION TA PACKAGE† ORDERABLE PART NUMBER TOP-...