SN74F161A

SN74F161A SYNCHRONOUS 4-BIT BINARY COUNTER SDFS056B – MARCH 1987 – REVISED AUGUST 2001 D Internal Look-Ahead Circuitry for Fast Counting D, DB, OR N PACKAGE (TOP VIEW) D Carry Output for N-Bit Cascading D Fully Synchronous Operation for Counting CLR 1 CLK 2 16 VCC 15 RCO description This synchronous, presettable, 4-bit binary counter has internal carry look-ahead circuitry for use in high-speed counting designs. A3 B4 C5 D6 ENP 7 14 QA 13 QB 12 QC 11 QD 10 ENT Synchronous operation is provided by having all GND 8 9 LOAD flip-flops clocked simultaneously so that the outputs change coincident with each other when so instructed by the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting spikes that are normally associated with asynchronous (ripple-clock) counters. However, counting spikes can occur on the ripple-carry (RCO) output. A buffered clock (CLK) input triggers the four flip-flops on the rising (positive-going) edge of CLK. This counter is fully programmable. That is, it can be preset to any number between 0 and 15. Because presetting is synchronous, a low logic level at the load (LOAD) input disables the counter and causes the outputs to agree with the setup data after the next clock pulse, regardless of the levels of ENP and ENT. The clear function is asynchronous, and a low logic level at the clear (CLR) input sets all four of the flip-flop outputs to low, regardless of the levels of CLK, LOAD, E...