SN74FB2033A

SN74FB2033A 8-BIT TTL/BTL REGISTERED TRANSCEIVER D Compatible With IEEE Std 1194.1-1991 (BTL) D TTL A Port, Backplane Transceiver Logic (BTL) B Port D Open-Collector B-Port Outputs Sink 100 mA D BIAS VCC Pin Minimizes Signal Distortion During Live Insertion or Withdrawal SCBS174M – NOVEMBER 1991 – REVISED SEPTEMBER 2001 D High-Impedance State During Power Up and Power Down D B-Port Biasing Network Preconditions the Connector and PC Trace to the BTL High-Level Voltage D TTL-Input Structures Incorporate Active Clamping Networks to Aid in Line Termination RC PACKAGE (TOP VIEW) AI2 AO1 AI1 GND VCC CLKAB/LEAB IMODE1 IMODE0 BG VCC OEA BG GND BIAS VCC B1 GND AO2 AI3 AO3 AI4 AO4 LOOPBACK AI5 AO5 AI6 AO6 AI7 GND 52 51 50 49 48 47 46 45 44 43 42 41 40 1 39 2 38 3 37 4 36 5 35 6 34 7 33 8 32 9 31 10 30 11 29 12 28 13 27 14 15 16 17 18 19 20 21 22 23 24 25 26 GND B2 GND B3 GND B4 GND B5 GND B6 GND B7 GND AO7 AI8 AO8 GND VCC CLKBA/LEBA OMODE0 OMODE1 VCC OEB OEB GND B8 description The SN74FB2033A is an 8-bit transceiver featuring a split input (AI) and output (AO) bus on the TTL-level A port. The common-I/O, open-collector B port operates at backplane transceiver logic (BTL) signal levels. The logic element for data flow in each direction is configured by two mode inputs (IMODE1 and IMODE0 for B-to-A, OMODE1 and OMODE0 for A-to-B) as a buffer, a D-type flip-flop, or a D-type latch. When configured in the buffer mode, the inverted input data appears at th...