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SN74LS165A Datasheet

Part Number SN74LS165A
Manufacturers Texas Instruments
Logo Texas Instruments
Description Parallel-Load 8-Bit Shift Registers
Datasheet SN74LS165A DatasheetSN74LS165A Datasheet (PDF)

The SN54165 and SN74165 devices are obsolete and are no longer supplied. SN54165, SN54LS165A, SN74165, SN74LS165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002 D Complementary Outputs D Direct Overriding Load (Data) Inputs D Gated Clock Inputs D Parallel-to-Serial Data Conversion TYPE ’165 ’LS165A TYPICAL MAXIMUM CLOCK FREQUENCY 26 MHz 35 MHz TYPICAL POWER DISSIPATION 210 mW 90 mW description The ’165 and ’LS165A are 8-bit serial shift registers that .

  SN74LS165A   SN74LS165A






Part Number SN74LS165
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description 8-Bit Parallel-to-Serial Shift Register
Datasheet SN74LS165A DatasheetSN74LS165 Datasheet (PDF)

SN74LS165 8−Bit Parallel−to−Serial Shift Register The SN74LS165 is an 8-bit parallel load or serial-in register with complementary outputs available from the last stage. Parallel inputing occurs asynchronously when the Parallel Load (PL) input is LOW. With PL HIGH, serial shifting occurs on the rising edge of the clock; new data enters via the Serial Data (DS) input. The 2-input OR clock can be used to combine two independent clock sources, or one input can act as an active LOW clock enable. G.

  SN74LS165A   SN74LS165A







Parallel-Load 8-Bit Shift Registers

The SN54165 and SN74165 devices are obsolete and are no longer supplied. SN54165, SN54LS165A, SN74165, SN74LS165A PARALLEL-LOAD 8-BIT SHIFT REGISTERS SDLS062D – OCTOBER 1976 – REVISED FEBRUARY 2002 D Complementary Outputs D Direct Overriding Load (Data) Inputs D Gated Clock Inputs D Parallel-to-Serial Data Conversion TYPE ’165 ’LS165A TYPICAL MAXIMUM CLOCK FREQUENCY 26 MHz 35 MHz TYPICAL POWER DISSIPATION 210 mW 90 mW description The ’165 and ’LS165A are 8-bit serial shift registers that shift the data in the direction of QA toward QH when clocked. Parallel-in access to each stage is made available by eight individual, direct data inputs that are enabled by a low level at the shift/load (SH/LD) input. These registers also feature gated clock (CLK) inputs and complementary outputs from the eighth bit. All inputs are diode-clamped to minimize transmission-line effects, thereby simplifying system design. Clocking is accomplished through a two-input positive-NOR gate, permitting one input to be used as a clock-inhibit function. Holding either of the clock inputs high inhibits clocking, and holding either clock input low with SH/LD high enables the other clock input. Clock inhibit (CLK INH) should be changed to the high level only while CLK is high. Parallel loading is inhibited as long as SH/LD is high. Data at the parallel inputs are loaded directly into the register while SH/LD is low, independently of the levels of CLK, CLK INH, or serial (SER) inputs. SN54165, SN54LS1.


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