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SN74LS748 Datasheet

Part Number SN74LS748
Manufacturers Motorola
Logo Motorola
Description 10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS
Datasheet SN74LS748 DatasheetSN74LS748 Datasheet (PDF)

10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are active at the low logic level. The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a.

  SN74LS748   SN74LS748






Part Number SN74LS74A
Manufacturers Texas Instruments
Logo Texas Instruments
Description Dual D-Type Positive-Edge Triggered Flip-Flops
Datasheet SN74LS748 DatasheetSN74LS74A Datasheet (PDF)

SN5474, SN54LS74A, SN54S74 SN7474. SN74LS74A, SN74S74 DUAL DĆTYPE POSITIVEĆEDGEĆTRIGGERED FLIPĆFLOPS WITH PRESET AND CLEAR SDLS119 − DECEMBER 1983 − REVISED MARCH 1988 PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. •POST OFFICE BOX 655303 DALLAS, TEXAS 75265 Copyright  1988, Texas Instruments Incorporated 1 SN54.

  SN74LS748   SN74LS748







Part Number SN74LS74A
Manufacturers Motorola
Logo Motorola
Description DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP
Datasheet SN74LS748 DatasheetSN74LS74A Datasheet (PDF)

DUAL D-TYPE POSITIVE EDGE-TRIGGERED FLIP-FLOP The SN54 / 74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going puls.

  SN74LS748   SN74LS748







Part Number SN74LS74A
Manufacturers ON Semiconductor
Logo ON Semiconductor
Description Dual D-Type Positive Edge-Triggered Flip-Flop
Datasheet SN74LS748 DatasheetSN74LS74A Datasheet (PDF)

SN74LS74A Dual D−Type Positive Edge−Triggered Flip−Flop The SN74LS74A dual edge-triggered flip-flop utilizes Schottky TTL circuitry to produce high speed D-type flip-flops. Each flip-flop has individual clear and set inputs, and also complementary Q and Q outputs. Information at input D is transferred to the Q output on the positive-going edge of the clock pulse. Clock triggering occurs at a voltage level of the clock pulse and is not directly related to the transition time of the positive-going.

  SN74LS748   SN74LS748







10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS

10-LINE-TO-4-LINE AND 8-LINE-TO-3-LINE PRIORITY ENCODERS The SN54 / 74LS147 and the SN54/ 74LS148 are Priority Encoders. They provide priority decoding of the inputs to ensure that only the highest order data line is encoded. Both devices have data inputs and outputs which are active at the low logic level. The LS147 encodes nine data lines to four-line (8-4-2-1) BCD. The implied decimal zero condition does not require an input condition because zero is encoded when all nine data lines are at a high logic level. The LS148 encodes eight data lines to three-line (4-2-1) binary (octal). By providing cascading circuitry (Enable Input EI and Enable Output EO) octal expansion is allowed without needing external circuitry. The SN54 / 74LS748 is a proprietary Motorola part incorporating a built-in deglitcher network which minimizes glitches on the GS output. The glitch occurs on the negative going transition of the EI input when data inputs 0 – 7 are at logical ones. The only dc parameter d.


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