SN74LV138AT

www.ti.com FEATURES Inputs Are TTL-Voltage Compatible 4.5-V to 5.5-V VCC Operation Max tpd of 7.6 ns at 5 V Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 5 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 5 V, TA = 25°C Support Mixed-Mode Voltage Operation on All Ports D, DB, DGV, NS, OR PW PACKAGE (TOP VIEW) A1 B2 C3 G2A 4 G2B 5 G1 6 Y7 7 GND 8 16 VCC 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 SN74LV138AT 3-LINE TO 8-LINE DECODER/DEMULTIPLEXER SCLS691 – AUGUST 2005 Ioff Supports Partial-Power Down Mode Operation Latch-Up Performance Exceeds 250 mA Per JESD 17 ESD Protection Exceeds JESD 22 – 2000-V Human-Body Model (A114-A) – 200-V Machine Model (A115-A) – 1000-V Charged-Device Model (C101) RGY PACKAGE (TOP VIEW) VCC A 1 B2 C3 G2A 4 G2B 5 G1 6 Y7 7 8 16 15 Y0 14 Y1 13 Y2 12 Y3 11 Y4 10 Y5 9 Y6 GND DESCRIPTION/ORDERING INFORMATION The SN74LV138AT is a 3-line to 8-line decoder/demultiplexer, designed for high-performance memory-decoding or data-routing applications requiring very short propagation delay times. In high-performance memory systems, this decoder can be used to minimize the effects of system decoding. When employed with high-speed memories utilizing a fast enable circuit, the delay times of the decoder and the enable time of the memory usually are less than the typical access time of the memory. This means that the effective system delay introduced by the decoder is negligible. TA –40°C to 125°C ORDERING INFORMATI...