COUNTER. SN74LV163A Datasheet

SN74LV163A Datasheet PDF

Part SN74LV163A
Description 4-BIT SYNCHRONOUS BINARY COUNTER
Feature SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS D 2-V to 5.5-V VCC Operation D Max tpd of .
Manufacture etcTI
Datasheet
Download SN74LV163A Datasheet

SN54LV163A, SN74LV163A 4-BIT SYNCHRONOUS BINARY COUNTERS D SN74LV163A Datasheet





SN74LV163A
SN54LV163A, SN74LV163A
4-BIT SYNCHRONOUS BINARY COUNTERS
D 2-V to 5.5-V VCC Operation
D Max tpd of 9.5 ns at 5 V
D Typical VOLP (Output Ground Bounce)
<0.8 V at VCC = 3.3 V, TA = 25°C
D Typical VOHV (Output VOH Undershoot)
>2.3 V at VCC = 3.3 V, TA = 25°C
D Support Mixed-Mode Voltage Operation on
All Ports
D Internal Look Ahead for Fast Counting
D Carry Output for n-Bit Cascading
SCLS405F − APRIL 1998 − REVISED APRIL 2005
D Synchronous Counting
D Synchronously Programmable
D Ioff Supports Partial-Power-Down Mode
Operation
D Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
D ESD Protection Exceeds JESD 22
− 2000-V Human-Body Model (A114-A)
− 200-V Machine Model (A115-A)
− 1000-V Charged-Device Model (C101)
SN54LV163A . . . J OR W PACKAGE
SN74LV163A . . . D, DB, DGV, NS,
OR PW PACKAGE
(TOP VIEW)
CLR 1
CLK 2
A3
B4
C5
D6
ENP 7
GND 8
16 VCC
15 RCO
14 QA
13 QB
12 QC
11 QD
10 ENT
9 LOAD
SN74LV163A . . . RGY PACKAGE
(TOP VIEW)
1
CLK 2
A3
B4
C5
D6
ENP 7
8
16
15 RCO
14 QA
13 QB
12 QC
11 QD
10 ENT
9
SN54LV163A . . . FK PACKAGE
(TOP VIEW)
3 2 1 20 19
A4
18 QA
B5
17 QB
NC 6
16 NC
C7
15 QC
D
8
14
9 10 11 12 13
QD
description/ordering information
NC − No internal connection
ORDERING INFORMATION
TA
PACKAGE
ORDERABLE
PART NUMBER
TOP-SIDE
MARKING
QFN − RGY
Reel of 1000 SN74LV163ARGYR LV163A
SOIC − D
Tube of 40
Reel of 2500
SN74LV163AD
SN74LV163ADR
LV163A
SOP − NS
Reel of 2000 SN74LV163ANSR
74LV163A
−40°C to 85°C
SSOP − DB
Reel of 2000
Tube of 90
SN74LV163ADBR
SN74LV163APW
LV163A
TSSOP − PW
Reel of 2000 SN74LV163APWR
LV163A
Reel of 250 SN74LV163APWT
TVSOP − DGV Reel of 2000 SN74LV163ADGVR LV163A
CDIP − J
Tube of 25
SNJ54LV163AJ
SNJ54LV163AJ
−55°C to 125°C CFP − W
Tube of 150 SNJ54LV163AW
SNJ54LV163AW
LCCC − FK
Tube of 55
SNJ54LV163AFK
SNJ54LV163AFK
Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines
are available at www.ti.com/sc/package.
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
UNLESS OTHERWISE NOTED this document contains PRODUCTION
DATA information current as of publication date. Products conform to
specifications per the terms of Texas Instruments standard warranty.
Production processing does not necessarily include testing of all
parameters.
POST OFFICE BOX 655303 DALLAS, TEXAS 75265
Copyright © 2005, Texas Instruments Incorporated
1



SN74LV163A
SN54LV163A, SN74LV163A
4-BIT SYNCHRONOUS BINARY COUNTERS
SCLS405F − APRIL 1998 − REVISED APRIL 2005
description/ordering information (continued)
The ’LV163A devices are 4-bit synchronous binary counters designed for 2-V to 5.5-V VCC operation.
These synchronous, presettable counters feature an internal carry look ahead for application in high-speed
counting designs. The ’LV163A devices are 4-bit binary counters. Synchronous operation is provided by having
all flip-flops clocked simultaneously so that the outputs change coincident with each other when instructed by
the count-enable (ENP, ENT) inputs and internal gating. This mode of operation eliminates the output counting
spikes normally associated with synchronous (ripple-clock) counters. A buffered clock (CLK) input triggers the
four flip-flops on the rising (positive-going) edge of the clock waveform.
These counters are fully programmable; that is, they can be preset to any number between 0 and 9 or 15. As
presetting is synchronous, setting up a low level at the load input disables the counter and causes the outputs
to agree with the setup data after the next clock pulse, regardless of the levels of the enable inputs.
The clear function for the ’LV163A devices is synchronous. A low level at the clear (CLR) input sets all four of
the flip-flop outputs low after the next low-to-high transition of CLK, regardless of the levels of the enable inputs.
This synchronous clear allows the count length to be modified easily by decoding the Q outputs for the maximum
count desired. The active-low output of the gate used for decoding is connected to CLR to synchronously clear
the counter to 0000 (LLLL).
The carry look-ahead circuitry provides for cascading counters for n-bit synchronous applications without
additional gating. ENP, ENT, and a ripple-carry output (RCO) are instrumental in accomplishing this function.
Both ENP and ENT must be high to count, and ENT is fed forward to enable RCO. Enabling RCO produces a
high-level pulse while the count is maximum (9 or 15 with QA high). This high-level overflow ripple-carry pulse
can be used to enable successive cascaded stages. Transitions at ENP or ENT are allowed, regardless of the
level of CLK.
These counters feature a fully independent clock circuit. Changes at control inputs (ENP, ENT, or LOAD) that
modify the operating mode have no effect on the contents of the counter until clocking occurs. The function of
the counter (whether enabled, disabled, loading, or counting) is dictated solely by the conditions meeting the
stable setup and hold times.
These devices are fully specified for partial-power-down applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow through the devices when they are powered down.
FUNCTION TABLE
INPUTS
OUTPUTS
CLR LOAD ENP ENT CLK QA QB QC QD
L
X
X
X
X
L
L
L
L
H
L
X
X
A
B
C
D
H
H
X
L
No change
H
H
L
X
No change
H
H
H
H
Count up
H
X
X
X
No change
FUNCTION
Reset to “0”
Preset data
No count
No count
Count
No count
2
POST OFFICE BOX 655303 DALLAS, TEXAS 75265




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