DatasheetsPDF.com

SN74LV27A Datasheet

Part Number SN74LV27A
Manufacturers Texas Instruments
Logo Texas Instruments
Description Triple 3-Input Positive-NOR Gate
Datasheet SN74LV27A DatasheetSN74LV27A Datasheet (PDF)

SN74LV27A SCES341F – SEPTEMBER 2000 – REVISED JULY 2023 SN74LV27A Triple 3-Input Positive-NOR Gate 1 Features • Operation of 2-V to 5.5-V VCC • Max tpd of 7 ns at 5 V • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C • Ioff Supports Partial-Power-Down Mode Operation • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II 2 Description These triple 3-input positive-NOR gates are designed for 2-V to.

  SN74LV27A   SN74LV27A






Part Number SN74LV273A
Manufacturers Texas Instruments
Logo Texas Instruments
Description Octal D-Type Flip-Flops
Datasheet SN74LV27A DatasheetSN74LV273A Datasheet (PDF)

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community SN74LV273A SCLS399K – APRIL 1998 – REVISED DECEMBER 2014 SN74LV273A Octal D-Type Flip-Flops With Clear 1 Features •1 2-V to 5.5-V VCC Operation • Max tpd of 10.5 ns at 5 V • Typical VOLP (Output Ground Bounce) < 0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) > 2.3 V at VCC = 3.3 V, TA = 25°C • Ioff Supports Partial-Power-Down Mode Operation • Supports Mixed-Mode Voltage Operation on.

  SN74LV27A   SN74LV27A







Triple 3-Input Positive-NOR Gate

SN74LV27A SCES341F – SEPTEMBER 2000 – REVISED JULY 2023 SN74LV27A Triple 3-Input Positive-NOR Gate 1 Features • Operation of 2-V to 5.5-V VCC • Max tpd of 7 ns at 5 V • Typical VOLP (Output Ground Bounce) <0.8 V at VCC = 3.3 V, TA = 25°C • Typical VOHV (Output VOH Undershoot) >2.3 V at VCC = 3.3 V, TA = 25°C • Ioff Supports Partial-Power-Down Mode Operation • Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II 2 Description These triple 3-input positive-NOR gates are designed for 2-V to 5.5-V VCC operation. The SN74LV27A devices perform the Boolean function Y = A + B + C in positive logic. These devices are fully specified for partial-powerdown applications using Ioff. The Ioff circuitry disables the outputs, preventing damaging current backflow through the devices when they are powered down. Package Information PART NUMBER PACKAGE1 PACKAGE SIZE2 DGV (TVSOP, 14) 3.60 mm x 6.4 mm D (SOIC, 14) 8.65 mm x 6 mm SN74LV27A NS (SO, 14) 10.20 mm x 7.8 mm DB (SSOP, 14) 6.20 mm x 7.8 mm PW (TSSOP, 14) 5.00 mm x 6.4 mm (1) For all available packages, see the orderable addendum at the end of the data sheet. (2) The package size (length × width) is a nominal value and includes pins, where applicable. \ xA xB xY xC Simplified Schematic An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications, intellectual property matters and other important disclaimers. UNLESS OTHERWISE NOTED, this documen.


2020-03-13 : LM5100    TAS5709A    TAS5707A    TAS5706B    TAS5707    FU6812    FT3107T    FT320    FD2105    FT3216   


@ 2014 :: Datasheetspdf.com ::
Semiconductors datasheet search & download site (Privacy Policy & Contact)