www.ti.com
SN74LVC16373A-EP 16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS825 – JUNE 2006
FEATURES
• Member...
www.ti.com
SN74LVC16373A-EP 16-BIT TRANSPARENT D-TYPE LATCH
WITH 3-STATE OUTPUTS
SCAS825 – JUNE 2006
FEATURES
Member of the Texas Instruments Widebus™ Family
Operates From 1.65 V to 3.6 V Inputs Accept
Voltages to 5.5 V Max tpd of 4.2 ns at 3.3 V Typical VOLP (Output Ground Bounce) <0.8 V
at VCC = 3.3 V, TA = 25°C Typical VOHV (Output VOH Undershoot) >2 V
at VCC = 3.3 V, TA = 25°C Ioff Supports Partial-Power-Down Mode
Operation
Supports Mixed-Mode Signal Operation (5-V Input and Output
Voltages With 3.3-V VCC)
Latch-Up Performance Exceeds 100 mA Per JESD 78, Class II
ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 1000-V Charged-Device Model (C101)
DESCRIPTION/ ORDERING INFORMATION
This 16-bit transparent D-type latch is designed for 1.65-V to 3.6-V VCC operation.
The SN74LVC16373A is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the D inputs.
DL PACKAGE (TOP VIEW)
1OE 1 1Q1 2 1Q2 3 GND 4 1Q3 5 1Q4 6 VCC 7 1Q5 8 1Q6 9 GND 10 1Q7 11 1Q8 12 2Q1 13 2Q2 14 GND 15 2Q3 16 2Q4 17 VCC 18 2Q5 19 2Q6 20 GND 21 2Q7 22 2Q8 23 2OE 24
48 1LE 47 1D1 46 1D2 45 GND 44 1D3 43 1D4 42 VCC 41 1D5 40 1D6 39 GND 38 1D7 37 1D8 36 2D1 35 2D2 34 GND 33 2D3 32 2D4 31 VCC...
