D-Type Flip-Flop. SN74LVC2G74 Datasheet

SN74LVC2G74 Datasheet PDF


Part Number

SN74LVC2G74

Description

Single Positive-Edge-Triggered D-Type Flip-Flop

Manufacture

etcTI

Total Page 25 Pages
Datasheet
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SN74LVC2G74
SCES203P – APRIL 1999 – REVISED JULY 2016
SN74LVC2G74 Single Positive-Edge-Triggered D-Type Flip-Flop
With Clear and Preset
1 Features
1 Available in the Texas Instruments
NanoFree™ Package
• Supports 5-V VCC Operation
• Inputs Accept Voltages to 5.5 V
• Max tpd of 5.9 ns at 3.3 V
• Low Power Consumption, 10-μA Max ICC
• ±24-mA Output Drive at 3.3 V
• Typical VOLP (Output Ground Bounce)
< 0.8 V at VCC = 3.3 V, TA = 25°C
• Typical VOHV (Output VOH Undershoot)
> 2 V at VCC = 3.3 V, TA = 25°C
• Ioff Supports Live Insertion, Partial-Power-Down
Mode, and Back-Drive Protection
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model
– 200-V Machine Model
– 1000-V Charged-Device Model
2 Applications
• Servers
• LED displays
• Network switch
• Telecom infrastructure
• Motor drivers
• I/O Expanders
3 Description
This single positive-edge-triggered D-type flip-flop is
designed for 1.65-V to 5.5-V VCC operation.
NanoFree™ package technology is a major
breakthrough in IC packaging concepts, using the die
as the package.
A low level at the preset (PRE) or clear (CLR) input
sets or resets the outputs, regardless of the levels of
the other inputs. When PRE and CLR are inactive
(high), data at the data (D) input meeting the setup
time requirements is transferred to the outputs on the
positive-going edge of the clock pulse. Clock
triggering occurs at a voltage level and is not related
directly to the rise time of the clock pulse. Following
the hold-time interval, data at the D input can be
changed without affecting the levels at the outputs.
This device is fully specified for partial-power-down
applications using Ioff. The Ioff circuitry disables the
outputs, preventing damaging current backflow
through the device when it is powered down.
Device Information(1)
PART NUMBER
PACKAGE
BODY SIZE
SM8 (8)
2.95 mm × 2.80 mm
SN74LVC2G74
VSSOP (8)
2.30 mm × 2.00 mm
DSBGA (8)
1.91 mm × 0.91 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Simplified Schematic
PRE
DQ
CLK Q
CLR
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.

SN74LVC2G74
SN74LVC2G74
SCES203P – APRIL 1999 – REVISED JULY 2016
www.ti.com
Table of Contents
1 Features .................................................................. 1
2 Applications ........................................................... 1
3 Description ............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions ......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings.............................................................. 4
6.3 Recommended Operating Conditions....................... 5
6.4 Thermal Information .................................................. 5
6.5 Electrical Characteristics........................................... 6
6.6 Timing Requirements, –40°C to +85°C..................... 6
6.7 Timing Requirements, –40°C to +125°C................... 6
6.8 Switching Characteristics, –40°C to +85°C............... 7
6.9 Switching Characteristics, –40°C to +125°C............. 7
6.10 Operating Characteristics........................................ 7
6.11 Typical Characteristics ............................................ 7
7 Parameter Measurement Information .................. 8
8 Detailed Description .............................................. 9
8.1 Overview ................................................................... 9
8.2 Functional Block Diagram ......................................... 9
8.3 Feature Description................................................... 9
8.4 Device Functional Modes.......................................... 9
9 Application and Implementation ........................ 10
9.1 Application Information .......................................... 10
9.2 Typical Power Button Circuit .................................. 10
10 Power Supply Recommendations ..................... 11
11 Layout................................................................... 12
11.1 Layout Guidelines ................................................. 12
11.2 Layout Example .................................................... 12
12 Device and Documentation Support ................. 13
12.1 Receiving Notification of Documentation Updates 13
12.2 Community Resources.......................................... 13
12.3 Trademarks ........................................................... 13
12.4 Electrostatic Discharge Caution ............................ 13
12.5 Glossary ................................................................ 13
13 Mechanical, Packaging, and Orderable
Information ........................................................... 13
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision O (January 2015) to Revision P
Page
• Changed SSOP to SM8 in Device Information table.............................................................................................................. 1
• Updated pinout images to new format.................................................................................................................................... 3
• Added pin number for DSBGA package in Pin Functions table ............................................................................................. 3
• Changed 6 PINS to 8 PINS in Thermal Information table ...................................................................................................... 5
• Changed 23 to 2.3 for tsu data in Timing Requirements, –40°C to +125°C ........................................................................... 6
• Added Receiving Notification of Documentation Updates section and Community Resources section .............................. 13
Changes from Revision N (July 2013) to Revision O
Page
• Added Applications, Device Information table, Pin Functions table, ESD Ratings table, Thermal Information table,
Typical Characteristics, Feature Description section, Device Functional Modes, Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................. 1
Changes from Revision M (February 2007) to Revision N
Page
• Changed Ioff description in Features....................................................................................................................................... 1
• Added parameter values for –40 to +125°C temperature ratings in Electrical Characteristics table. .................................... 6
• Changed Timing Requirements, –40°C to +85°C table.......................................................................................................... 6
• Added Timing Requirements, –40°C to +125°C table............................................................................................................ 6
• Changed Switching Characteristics, –40°C to +85°C table.................................................................................................... 7
• Added Switching Characteristics, –40°C to +125°C table...................................................................................................... 7
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