26-BIT REGISTERED BUFFER
|Total Page||11 Pages|
|Features||Datasheet pdf www.ti.com SN74SSTV32867-EP 26-BIT REGI STERED BUFFER WITH SSTL_2 INPUTS AND LV CMOS OUTPUTS SCES664 – SEPTEMBER 2006 FEATURES • Controlled Baseline – One Assembly/Test Site, One Fabricatio n Site • Extended Temperature Perform ance of –40°C to 85°C • Enhanced Diminishing Manufacturing Sources (DMS) Support • Enhanced Product Change No tification • Qualification Pedigree ( 1) • Member of the Texas Instruments Widebus+™ Family (1) Component qualif ication in accordance with JEDEC and in dustry standards to ensure reliable ope ration over an extended temperature ran ge. This includes, but is not limited t o, Highly Accelerated Stress Test (HAST ) or biased 85/85, temperature cycle, a utoclave or unbiased HAST, electromigra tion, bond intermetallic life, and mold compound life. Such qualification test ing should not be viewed as justifying use of this component beyond specified performance and environmental limits. • Output Edge-Control Circuitry Minimizes Switching Noise in an Unterminated DIMM Loa.|
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26-BIT REGISTERED BUFFER
WITH SSTL_2 INPUTS AND LVCMOS OUTPUTS
SCES664 – SEPTEMBER 2006
• Controlled Baseline
– One Assembly/Test Site, One Fabrication
• Extended Temperature Performance of –40°C
• Enhanced Diminishing Manufacturing
Sources (DMS) Support
• Enhanced Product Change Notification
• Qualification Pedigree (1)
• Member of the Texas Instruments
(1) Component qualification in accordance with JEDEC and
industry standards to ensure reliable operation over an
extended temperature range. This includes, but is not limited
to, Highly Accelerated Stress Test (HAST) or biased 85/85,
temperature cycle, autoclave or unbiased HAST,
electromigration, bond intermetallic life, and mold compound
life. Such qualification testing should not be viewed as
justifying use of this component beyond specified
performance and environmental limits.
• Output Edge-Control Circuitry Minimizes
Switching Noise in an Unterminated DIMM
• Supports SSTL_2 Data Inputs
• Differential Clock (CLK and CLK) Inputs
• Supports LVCMOS Switching Levels on the
• RESET Input Disables Differential Input
Receivers, Resets All Registers, and Forces
All Outputs Low
• Latch-Up Performance Exceeds 100 mA Per
JESD 78, Class II
• ESD Protection Exceeds JESD 22
– 2000-V Human-Body Model (A114-A)
– 200-V Machine Model (A115-A)
– 1000-V Charged-Device Model (C101)
This 26-bit registered buffer is designed for 2.3-V to 2.7-V VCC operation.
All inputs are SSTL_2, except the LVCMOS reset (RESET) input. All outputs are edge-controlled LVCMOS
circuits optimized for unterminated DIMM loads.
The SN74SSTV32867-EP operates from a differential clock (CLK and CLK). Data are registered at the crossing
of CLK going high and CLK going low.
The device supports low-power standby operation. When RESET is low, the differential input receivers are
disabled, and undriven (floating) data, clock, and reference voltage (VREF) inputs are allowed. In addition, when
RESET is low, all registers are reset and all outputs are forced low. The LVCMOS RESET always must be held
at a valid logic high or low level.
To ensure defined outputs from the register before a stable clock has been supplied, RESET must be held in the
low state during power up.
–40°C to 85°C
LFBGA – GKE
Tape and reel
ORDERABLE PART NUMBER
(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are available at
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas
Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
Widebus+ is a trademark of Texas Instruments.
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
Copyright © 2006, Texas Instruments Incorporated
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