SPC564A74B4, SPC564A74L7, SPC564A80B4, SPC564A80L7
32-bit MCU family built on the embedded Power Architecture®
Features
■ 150 MHz e200z4 Power Architecture® core – Variable length instruction encoding (VLE) – Superscalar architecture with 2 execution units – Up to 2 integer or floating point instructions per cycle – Up to 4 multiply and accumulate operations per cycle
■ Memory organization – 4 MB on-chip flash memory with ECC and Read While Write (RWW) – 192 KB on-chip RAM with standby functio.
32-bit MCU
SPC564A74B4, SPC564A74L7, SPC564A80B4, SPC564A80L7
32-bit MCU family built on the embedded Power Architecture®
Features
■ 150 MHz e200z4 Power Architecture® core – Variable length instruction encoding (VLE) – Superscalar architecture with 2 execution units – Up to 2 integer or floating point instructions per cycle – Up to 4 multiply and accumulate operations per cycle
■ Memory organization – 4 MB on-chip flash memory with ECC and Read While Write (RWW) – 192 KB on-chip RAM with standby functionality (32 KB) and ECC – 8 KB instruction cache (with line locking), configurable as 2- or 4-way – 14 + 3 KB eTPU code and data RAM – 5 4 crossbar switch (XBAR) – 24-entry MMU – External Bus Interface (EBI) with slave and master port
■ Fail Safe Protection – 16-entry Memory Protection Unit (MPU) – CRC unit with 3 sub-modules – Junction temperature sensor
■ Interrupts – Configurable interrupt controller (with NMI) – 64-channel DMA
■ Serial channels – 3 eSCI – 3 DSPI (2 of which support downstream Micro Second Channel [MSC])
Table 1. Device summary
LBGA208
PBGA324
LQFP176
– 3 FlexCAN with 64 messages each
– 1 FlexRay module (V2.1) up to 10 Mbit/s with dual or single channel and 128 message objects and ECC
■ 1 eMIOS
■ 1 eTPU2 (second generation eTPU)
■ 2 enhanced queued analog-to-digital converters (eQADCs)
■ On-chip CAN/SCI/FlexRay Bootstrap loader with Boot Assist Module (BAM)
■ Nexus: Class 3+ for core; Class 1 for the eTPU
■ JTAG (5-pin)
■ Development Trigger .