SSI1N50B

SSW1N50B / SSI1N50B SSW1N50B / SSI1N50B 520V N-Channel MOSFET General Description These N-Channel enhancement mode power field effect transistors are produced using Fairchild’s proprietary, www.DataSheet4U.com planar, DMOS technology. This advanced technology has been especially tailored to minimize on-state resistance, provide superior switching performance, and withstand high energy pulse in the avalanche and commutation mode. These devices are well suited for high efficiency switch mode power supplies, power factor correction and electronic lamp ballasts based on half bridge. Features 1.5A, 520V, RDS(on) = 5.3Ω @VGS = 10 V Low gate charge ( typical 8.3 nC) Low Crss ( typical 5.5 pF) Fast switching 100% avalanche tested Improved dv/dt capability D D ! ● ◀ ▲ ● ● G S D2-PAK SSW Series G D S I2-PAK SSI Series G! ! S Absolute Maximum Ratings Symbol VDSS ID IDM VGSS EAS IAR EAR dv/dt PD TC = 25°C unless otherwise noted Parameter Drain-Source Voltage - Continuous (TC = 25°C) Drain Current - Continuous (TC = 100°C) Drain Current - Pulsed (Note 1) SSW1N50B / SSI1N50B 520 1.5 0.97 5.0 ± 30 (Note 2) (Note 1) (Note 1) (Note 3) Units V A A A V mJ A mJ V/ns W W W/°C °C °C Gate-Source Voltage Single Pulsed Avalanche Energy Avalanche Current Repetitive Avalanche Energy Peak Diode Recovery dv/dt Power Dissipation (TA = 25°C) * 100 1.5 3.6 5.5 3.13 36 0.29 -55 to +150 300 TJ, Tstg TL Power Dissipation (TC = 25°C) - Derate above 25°C Operating and Storage T...