SSTE32882HLB

DATASHEET 1.35V/1.5V REGISTERING CLOCK DRIVER WITH PARITY TEST AND QUAD CHIP SELECT SSTE32882HLB Description This 28-bit 1:2, or 26-bit 1:2 and 4-bit 1:1, registering clock driver with parity is designed for 1.35V and 1.5V VDD operation. All inputs are 1.35V and 1.5V CMOS compatible, except the reset (RESET) and MIRROR inputs which are LVCMOS. All outputs are 1.35V and 1.5V CMOS edge-controlled drivers optimized to drive single terminated 25 to 50 traces in DDR3 RDIMM applications, except the open-drain error (ERROUT) output. The clock outputs (Yn and Yn) and control net outputs QnCKEn, QnCSn and QnODTn are designed with a different strength and skew to compensate for different loading and equalize signal travel speed. The SSTE32882HLB has two basic modes of operation associated with the Quad Chip Select Enable (QCSEN) input. When the QCSEN input pin is open (or pulled high), the component has two chip select inputs, DCS0 and DCS1, and two copies of each chip select output, QA...