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SSTUH32866 Datasheet

Part Number SSTUH32866
Manufacturers NXP
Logo NXP
Description 1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer
Datasheet SSTUH32866 DatasheetSSTUH32866 Datasheet (PDF)

SSTUH32866 Rev. 01 — 13 May 2005 www.DataSheet4U.com 1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2 RDIMM applications Product data sheet 1. General description The SSTUH32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in .

  SSTUH32866   SSTUH32866






Part Number SSTUH32865
Manufacturers NXP
Logo NXP
Description 1.8V 28-bit high output drive 1:2 registered buffer
Datasheet SSTUH32866 DatasheetSSTUH32865 Datasheet (PDF)

SSTUH32865 1.8 V 28-bit high output drive 1:2 registered buffer with parity for DDR2 RDIMM applications Rev. 01 — 11 March 2005 Product data sheet 1. General description The SSTUH32865 is a 1.8 V 28-bit high output drive 1:2 register specifically designed for use on two rank by four (2R × 4) and similar high-density Double Data Rate 2 (DDR2) memory modules. It is similar in function to the JEDEC-standard 14-bit DDR2 register, but integrates the functionality of the normally required two register.

  SSTUH32866   SSTUH32866







Part Number SSTUH32864
Manufacturers NXP
Logo NXP
Description 1.8 V high output drive configurable registered buffer
Datasheet SSTUH32866 DatasheetSSTUH32864 Datasheet (PDF)

SSTUH32864 Rev. 01 — 22 April 2005 www.DataSheet4U.com 1.8 V high output drive configurable registered buffer for DDR2 RDIMM applications Product data sheet 1. General description The SSTUH32864 is a 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer designed for 1.7 V to 1.9 V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load.

  SSTUH32866   SSTUH32866







1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer

SSTUH32866 Rev. 01 — 13 May 2005 www.DataSheet4U.com 1.8 V high output drive 25-bit 1 : 1 or 14-bit 1 : 2 configurable registered buffer with parity for DDR2 RDIMM applications Product data sheet 1. General description The SSTUH32866 is a 1.8 V configurable register specifically designed for use on DDR2 memory modules requiring a parity checking function. It is defined in accordance with the JEDEC JESD82-7 standard for the SSTU32864 registered buffer, while adding the parity checking function in a compatible pinout. The JEDEC standard for SSTUH32866 is pending publication. The register is configurable (using configuration pins C0 and C1) to two topologies: 25-bit 1 : 1 or 14-bit 1 : 2, and in the latter configuration can be designated as Register A or Register B on the DIMM. The SSTUH32866 accepts a parity bit from the memory controller on its parity bit (PAR_IN) input, compares it with the data received on the DIMM-independent D-inputs and indicates whether a parity error has occurred on its open-drain QERR pin (active LOW). The convention is even parity, that is, valid parity is defined as an even number of ones across the DIMM-independent data inputs combined with the parity input bit. The SSTUH32866 is packaged in a 96-ball, 6 × 16 grid, 0.8 mm ball pitch LFBGA package (13.5 mm × 5.5 mm). The SSTUH32866 is identical to SSTU32866 in function and performance, with higher-drive outputs optimized to drive heavy load nets (for example, stacked DRAMs) while maintaining speed and sig.


2010-06-15 : IXTQ74N20P    IXTT74N20P    IXFR64N50P    IXFX64N50P    IXFK64N50P    IXFR36N60P    SSTUH32864    SSTUH32866    SC68C652B    K1S3216BCC   


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