STD412S

STU/D412S S a mHop Microelectronics C orp. Ver 1.0 N-Channel Logic Level Enhancement Mode Field Effect Transistor PRODUCT SUMMARY V DSS 40V FEATURES Super high dense cell design for low R DS(ON). Rugged and reliable. TO-252 and TO-251 Package. ID 22A R DS(ON) (m Ω) Max 26 @ VGS=10V 40 @ VGS=4.5V ESD Protected. D D G S G D G S STU SERIES TO-252AA(D-PAK) STD SERIES TO-251(l-PAK) S ABSOLUTE Symbol VDS VGS ID IDM EAS PD TJ, TSTG MAXIMUM RATINGS ( T C=25 °C unless otherwise noted ) Parameter Drain-Source Voltage Gate-Source Voltage TA=25 °C a Drain Current-Continuous TA=70 °C -Pulsed b Avalanche Energy c Limit 40 ±20 22 17.5 80 10 25 16 -55 to 150 Units V V A A A mJ W W °C Maximum Power Dissipation a TA=25 °C TA=70 °C Operating Junction and Storage Temperature Range THERMAL CHARACTERISTICS R JC R JA Thermal Resistance, Junction-to-Case a Thermal Resistance, Junction-to-Ambient a 5 50 °C/W °C/W Aug,07,2008 1 www.samhop.com.tw Downloaded from Elcodis.com electronic components distributor STU/D412S Ver 1.0 ELECTRICAL CHARACTERISTICS ( T C=25 °C unless otherwise noted ) Symbol Parameter Conditions VGS=0V , ID=250uA VDS=32V , VGS=0V Min 40 Typ Max Units V OFF CHARACTERISTICS Drain-Source Breakdown Voltage BVDSS Zero Gate Voltage Drain Current IDSS Gate-Body leakage current IGSS ON CHARACTERISTICS VGS(th) Gate Threshold Voltage RDS(ON) gFS Drain-Source On-State Resistance Forward Transconductance b a VGS= ±20V , VDS=0V 1 ±10 3 26 40 A uA VDS=VGS , ID=...