P-Channel Logic Level Enhancement Mode Field Effect Transistor
Description
S T U/D421S
S amHop Microelectronics C orp.
Aug.20,2006
P -C hannel Logic Level E nhancement Mode Field E ffect Transistor
P R ODUC T S UMMAR Y
V DS S
-40V
F E AT UR E S
( m W ) Max
ID
-10A
R DS (ON)
S uper high dense cell design for low R DS (ON ).
45 @ V G S = -10V 60 @ V G S = -4.5V
R ugged and reliable. TO-252 and TO-251 P ackage.
D
D G S
G D
S...
