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SY87721L Datasheet

Part Number SY87721L
Manufacturers Micrel Semiconductor
Logo Micrel Semiconductor
Description 3.3V 28Mbps-2.7Gbps ANYRATE CLOCK AND DATA RECOVERY
Datasheet SY87721L DatasheetSY87721L Datasheet (PDF)

Micrel, Inc. 3.3V 28Mbps-2.7Gbps AnyRate® CLOCK AND DATA RECOVERY WITH INTEGRATED CLOCK MULTIPLIER UNIT DESCRIPTION SY87721L SY87721L FEATURES s Recovers any data and clock from 28Mbps to 2.7Gbps • OC-1, OC-3, OC-12, OC-48, ATM • Gigabit Ethernet, Fast Ethernet • Fibre Channel, 2x Fibre Channel • P1394, Infiniband • SMPTE-259, SMPTE-292 • Proprietary optical transport s Integrated clock multiplier unit with low jitter generation s Complies with Bellcore, ITU/CCITT and ANSI specifications s S.

  SY87721L   SY87721L






3.3V 28Mbps-2.7Gbps ANYRATE CLOCK AND DATA RECOVERY

Micrel, Inc. 3.3V 28Mbps-2.7Gbps AnyRate® CLOCK AND DATA RECOVERY WITH INTEGRATED CLOCK MULTIPLIER UNIT DESCRIPTION SY87721L SY87721L FEATURES s Recovers any data and clock from 28Mbps to 2.7Gbps • OC-1, OC-3, OC-12, OC-48, ATM • Gigabit Ethernet, Fast Ethernet • Fibre Channel, 2x Fibre Channel • P1394, Infiniband • SMPTE-259, SMPTE-292 • Proprietary optical transport s Integrated clock multiplier unit with low jitter generation s Complies with Bellcore, ITU/CCITT and ANSI specifications s Selectable mux for pass through; avoids jitter accumulation when switching through backplanes s Available in 64-Pin EPAD-TQFP package The SY87721L is a complete Clock Recovery and Data retiming integrated circuit for data rates from 28Mbps up to 2.7Gbps NRZ including SONET FEC data rates. Included in the device, is a fully integrated Clock Multiplier Unit (CMU) that is capable of generating frequencies that cover the same data rate range as the CDR. The device is ideally suited for SONET/SDH/ATM, Fibre Channel, and Gigabit Ethernet applications, as well as other high-speed data transmission applications. Clock recovery and data retiming is performed by synchronizing the on-chip VCO directly to the incoming data stream. The VCO center frequency is controlled by the reference clock frequency and the selected divide ratio. On-chip clock generation is performed through the use of a frequency multiplier PLL with a byte rate or code group rate source as reference. SIMPLIFIED BLOCK DIAGRAM S.


2010-01-08 : MKP    SY87721L    R8400-xxPD-Y    IKW25N120T2    75NF20    C1096    NTE637    HD74UH4066    UH4PBC    UH4PCC   


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