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SY89808L Datasheet

Part Number SY89808L
Manufacturers Micrel Semiconductor
Logo Micrel Semiconductor
Description 1:9 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR
Datasheet SY89808L DatasheetSY89808L Datasheet (PDF)

Micrel, Inc. 3.3V, 500MHz, 1:9 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/ TRANSLATOR Precision Edge® ® SY89808L Precision Edge SY89808L FEATURES s 9 differential HSTL (1.5V compatible) output pairs s 500MHz maximum clock frequency s Triple-buffered enable function s 3.3V core supply, 1.8V output supply for reduced s s s s s Precision Edge® DESCRIPTION power LVPECL and HSTL inputs HSTL outputs drive 50Ω to ground with no offset voltage Low pin-to-pin skew (25ps max.) Guaranteed over industria.

  SY89808L   SY89808L






1:9 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/TRANSLATOR

Micrel, Inc. 3.3V, 500MHz, 1:9 DIFFERENTIAL HSTL (1.5V) FANOUT BUFFER/ TRANSLATOR Precision Edge® ® SY89808L Precision Edge SY89808L FEATURES s 9 differential HSTL (1.5V compatible) output pairs s 500MHz maximum clock frequency s Triple-buffered enable function s 3.3V core supply, 1.8V output supply for reduced s s s s s Precision Edge® DESCRIPTION power LVPECL and HSTL inputs HSTL outputs drive 50Ω to ground with no offset voltage Low pin-to-pin skew (25ps max.) Guaranteed over industrial –40°C to +85°C temperature range Available in 32-pin TQFP package APPLICATIONS s Workstations s Parallel processor-based systems s High-performance computing s Communications The SY89808L is a High-Performance Bus Clock Driver with 9 differential HSTL (High-Speed Transceiver Logic) 1.5V compatible output pairs. The part is designed for use in lowvoltage (3.3V/1.8V) applications which require a large number of outputs to drive precisely aligned, ultra-low skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the CLK_SEL pin. The Output Enable (OE) is synchronous and triple-buffered so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any potential of generating a runt clock pulse when the device is enabled/disabled, as can occur with an asynchronous control. The triple-buffering feature provides a three-clock delay from the time the OE input is asserted/d.


2007-05-02 : 2SA2151    2SA2151A    2SC6011    2SC6011A    8904    A3989    A3992    A3995    A5338    A8292   


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