SY89872U

Micrel, Inc. Precision Edge 2.5V, 2GHz ANY DIFF. IN-TO-LVDS SY89872U ® PROGRAMMABLE CLOCK DIVIDER/FANOUT Precision Edge SY89872U BUFFER WITH INTERNAL TERMINATION ® FEATURES ■ Guaranteed AC performance over temperature and Precision Edge® voltage: >2GHz fMAX < 750ps tPD (matched delay between banks) DESCRIPTION < 15ps within-device skew < 200ps rise/fall time This 2.5V low-skew, low-jitter, precision LVDS output clock ■ Low jitter design divider accepts any high-speed differential clock input (AC < 1psRMS cycle-to-cycle jitter or DC-coupled) CML, LVPECL, HSTL or LVDS and divides < 10psPP total jitter down the frequency using a programmable divider ratio to create a frequency-locked, lower speed version of the input ■ Unique input termination and VT pin for DC-coupled clock. The SY89872U includes two output banks. Bank A is and AC-coupled inputs: any differential inputs an exact copy of the input clock (pass through) with matched (LVPECL, LVDS, CML, HSTL) propagation delay to Bank B, the divided output bank. ■ Precision differential LVDS outputs Available divider ratios are 2, 4, 8 and 16. In a typical ■ Matched delay: all outputs have matched delay, 622MHz clock system this would provide availability of independent of divider setting 311MHz, 155MHz, 77MHz or 38MHz auxiliary clock ■ TTL/CMOS inputs for select and reset/disable components. The differential input buffer has a unique internal ■ Two output banks (matched delay) termination design that allows access t...