Si5347/46
D UAL/ Q UAD D S P L L A NY- F REQUENCY, A NY- O UTPUT J ITTER A TTENUATORS
Si5347C/D
Features
Four or t...
Si5347/46
D UAL/ Q UAD D S P L L A NY- F REQUENCY, A NY- O UTPUT J ITTER A TTENUATORS
Si5347C/D
Features
Four or two independent DSPLLs in a Automatic free-run and holdover modes
single monolithic IC
Fastlock feature for low nominal
Each DSPLL generates any output
bandwidths
frequency from any input frequency Input frequency range:
Glitchless on-the-fly DSPLL frequency changes
Differential: 8 kHz to 750 MHz
DCO mode: as low as 0.01 ppb steps
LV
CMOS: 8 kHz to 250 MHz Output frequency range:
per DSPLL Core
voltage:
Differential: up to 712.5 MHz
VDD: 1.8 V ±5%
LV
CMOS: up to 250 MHz Ultra low jitter:
VDDA: 3.3 V ±5% Independent output clock supply pins:
<100 fs typ (12 kHz–20 MHz)
3.3, 2.5, or 1.8 V
Flexible crosspoints route any input to Output-output skew:
any output clock
<20 ps (typ) per DSPLL
Programmable jitter attenuation bandwidth per DSPLL: 0.1 Hz to 4 kHz programming range Highly configurable outputs compatible with LVDS, LVPECL, LV
CMOS, CML,
Serial interface: I2C or SPI In-circuit programmable with non-volatile OTP memory ClockBuilderTM Pro software tool
and HCSL with programmable signal
simplifies device configuration
amplitude
Si5347: Quad DSPLL, 4 input,
Status monitoring (LOS, OOF, LOL)
4 or 8 output, 64 QFN
Hitless input clock switching: automatic Si5346: Dual DSPLL, 4 input,
or manual Locks to gapped clock inputs
4 output, 44 QFN Temperature range: –40 to +85 °C Pb...