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TC511001J-12 Datasheet

TOSHIBA MOS MEMORY PRODUCT 1,048,576 WORDS X 1 BIT DYNAMIC RAM SILICON GATE CMOS DESCRIPTION TC511001 P/J/Z-S5, TC511001 P/J/Z-l0 TC511 001 P/J/Z-12 The TC5ll00lP/J/Z is the new generation dynamic R&~ organized 1,048,576 ~vords by 1 bit. The TC5ll00lP/J/Z utilizes TOSHIBA's caos Silicon gate process technology as well as adva.

Toshiba
TC511001J-12.pdf

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Toshiba TC511001J-12 Datasheet
TOSHIBA MOS MEMORY PRODUCT 1,048,576 WORDS X 1 BIT DYNAMIC RAM SILICON GATE CMOS DESCRIPTION TC511001 P/J/Z-S5, TC511001 P/J/Z-l0 TC511 001 P/J/Z-12 The TC5ll00lP/J/Z is the new generation dynamic R&~ organized 1,048,576 ~vords by 1 bit. The TC5ll00lP/J/Z utilizes TOSHIBA's caos Silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the system user. Multiplexed address inputs permit the TC5ll00lP/J/Z to be packaged in a standard 18 pin plastic DIP, 26/20 pin plastic SOJ and 20/19 pin plastic ZIP. The package size provides high system bit "densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply of 5V±10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. The special feature of TC5Il00IP/J/Z is nibble mode, allowing the user to serially access 4 bits of data at a high data r.






TOSHIBA MOS MEMORY PRODUCT 1,048,576 WORDS X 1 BIT DYNAMIC RAM SILICON GATE CMOS DESCRIPTION TC511001 P/J/Z-S5, TC511001 P/J/Z-l0 TC511 001 P/J/Z-12 The TC5ll00lP/J/Z is the new generation dynamic R&~ organized 1,048,576 ~vords by 1 bit. The TC5ll00lP/J/Z utilizes TOSHIBA's caos Silicon gate process technology as well as adva.

Toshiba
TC511001J-12.pdf

Preview

Preview
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Toshiba TC511001J-12 Datasheet
TOSHIBA MOS MEMORY PRODUCT 1,048,576 WORDS X 1 BIT DYNAMIC RAM SILICON GATE CMOS DESCRIPTION TC511001 P/J/Z-S5, TC511001 P/J/Z-l0 TC511 001 P/J/Z-12 The TC5ll00lP/J/Z is the new generation dynamic R&~ organized 1,048,576 ~vords by 1 bit. The TC5ll00lP/J/Z utilizes TOSHIBA's caos Silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the system user. Multiplexed address inputs permit the TC5ll00lP/J/Z to be packaged in a standard 18 pin plastic DIP, 26/20 pin plastic SOJ and 20/19 pin plastic ZIP. The package size provides high system bit "densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply of 5V±10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. The special feature of TC5Il00IP/J/Z is nibble mode, allowing the user to serially access 4 bits of data at a high data r.






DRAM

TOSHIBA MOS MEMORY PRODUCT 1,048,576 WORDS X 1 BIT DYNAMIC RAM SILICON GATE CMOS DESCRIPTION TC511001 P/J/Z-S5, TC511001 P/J/Z-l0 TC511 001 P/J/Z-12 The TC5ll00lP/J/Z is the new generation dynamic R&~ organized 1,048,576 ~vords by 1 bit. The TC5ll00lP/J/Z utilizes TOSHIBA's caos Silicon gate process technology as well as advanced circuit techniques to provide wide operating margins, both internally and to the system user. Multiplexed address inputs permit the TC5ll00lP/J/Z to be packaged in a standard 18 pin plastic DIP, 26/20 pin plastic SOJ and 20/19 pin plastic ZIP. The package size provides high system bit "densities and is compatible with widely available automated testing and insertion equipment. System oriented features include single power supply of 5V±10% tolerance, direct interfacing capability with high performance logic families such as Schottky TTL. The special feature of TC5Il00IP/J/Z is nibble mode, allowing the user to serially access 4 bits of data at a high data r.


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