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TC55BS4258J-12 Datasheet

Part Number TC55BS4258J-12
Manufacturers Toshiba
Logo Toshiba
Description 256K x 4-Bit Synchronous Static RAM
Datasheet TC55BS4258J-12 DatasheetTC55BS4258J-12 Datasheet (PDF)

TOSHIBA 262,144 WORD x 4 BIT SYNCHRONOUS STATIC RAM with Input Registers, Output Registers and Pass-Through Feature 1l:55BS4258]-10/12 PRELIMINARY Description The TC55BS4258J is a 1,048,576 bit synchronous static random access memory fabricated using BiCMOS technology and organized as 262,144 words by 4 bits. The TC55BS4258J has separate data inputs and outputs and a write-cycle pass-through feature. Designed for pipelined architectures, this device has internal input and output registers whi.

  TC55BS4258J-12   TC55BS4258J-12






Part Number TC55BS4258J-10
Manufacturers Toshiba
Logo Toshiba
Description 256K x 4-Bit Synchronous Static RAM
Datasheet TC55BS4258J-12 DatasheetTC55BS4258J-10 Datasheet (PDF)

TOSHIBA 262,144 WORD x 4 BIT SYNCHRONOUS STATIC RAM with Input Registers, Output Registers and Pass-Through Feature 1l:55BS4258]-10/12 PRELIMINARY Description The TC55BS4258J is a 1,048,576 bit synchronous static random access memory fabricated using BiCMOS technology and organized as 262,144 words by 4 bits. The TC55BS4258J has separate data inputs and outputs and a write-cycle pass-through feature. Designed for pipelined architectures, this device has internal input and output registers whi.

  TC55BS4258J-12   TC55BS4258J-12







256K x 4-Bit Synchronous Static RAM

TOSHIBA 262,144 WORD x 4 BIT SYNCHRONOUS STATIC RAM with Input Registers, Output Registers and Pass-Through Feature 1l:55BS4258]-10/12 PRELIMINARY Description The TC55BS4258J is a 1,048,576 bit synchronous static random access memory fabricated using BiCMOS technology and organized as 262,144 words by 4 bits. The TC55BS4258J has separate data inputs and outputs and a write-cycle pass-through feature. Designed for pipelined architectures, this device has internal input and output registers which latch on the positive edge of an external clock (ClK). All address, data, and control signals are latched. The setup and hold times for the inputs are 2ns and 1ns respectively. Synchronous SRAMs can lead to faster, more robust system operation by virtually eliminating the timing skew problems associated with conventional asynchronous SRAMs. For example, write operations are internally self-timed when initiated - eliminating the need for accurate write pulse generation and timing by the memory.


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