Core Logic
7'[
$0,+* PLFURQ &026 *DWH $UUD\
Description TD0x is a family of non-inverting time delays.
Logic Symbol
Truth Table
TD0x
Delay
AQ LL HH
HDL Syntax Verilog .................... TD0x inst_name (Q, A); VHDL...................... inst_name: TD0x port map (Q, A);
Pin Loading Pin Name A
TD02 1.5
Equivalent Loads TD03 1.0
TD08 1.0
Si...
