TDA8754

INTEGRATED CIRCUITS DATA SHEET TDA8754 Triple high speed ADC for LCD drive Objective specification File under Integrated Circuits, IC02 1998 Sep 30 Philips Semiconductors Objective specification Triple high speed ADC for LCD drive FEATURES Triple 8-bit Analog-to-Digital Converter (ADC) Sampling rate up to 170 MHz IC controllable via a serial interface, which can be either I2C-bus or 3-wire, selected via a TTL input pin IC analog input 0.5 to 1.1 V (peak-to-peak value) to have full-scale ADC input Clamps for programming a clamp level through a clamping code between −63 and +64 by steps of 1 LSB Controllable gain stages: gain controlled independently on the 3 channels via the serial interface to have a full-scale resolution to 1% Low gain variation at different temperatures Analog bandwidth of 400 MHz Controllable PLL via the serial interface generates the ADC clock. It can be locked on line frequencies from 15 kHz up to 280 kHz. Integrated PLL divider Integrated clamp pulse and H and V LCD control pulses generation (independently adjustable in position and duration). Also a data enable signal can be generated, independently adjustable in position and duration with respect to HSYNC. The pixel clock is available at half the clock frequency Programmable phase clock adjustment cells Internal voltage regulators TTL compatible digital inputs 3.3 V CMOS compatible digital outputs Outputs: one port output up to 140 MHz or 2-port demultiplexed outpu...