TL16C554I

ąą TL16C554, TL16C554I ASYNCHRONOUS COMMUNICATIONS ELEMENT ą SLLS165G − JANUARY 1994 − REVISED MARCH 2006 D Integrated Asynchronous Communications Element D Consists of Four Improved TL16C550 ACEs Plus Steering Logic D In FIFO Mode, Each ACE Transmitter and Receiver Is Buffered With 16-Byte FIFO to Reduce the Number of Interrupts to CPU D In TL16C450 Mode, Hold and Shift Registers Eliminate Need for Precise Synchronization Between the CPU and Serial Data D Up to 16-MHz Clock Rate for up to 1-Mbaud Operation D Programmable Baud Rate Generators Which Allow Division of Any Input Reference Clock by 1 to (216ā −ā 1) and Generate an Internal 16 × Clock D Adds or Deletes Standard Asynchronous Communication Bits (Start, Stop, and Parity) to or From the Serial Data Stream D Independently Controlled Transmit, Receive, Line Status, and Data Set Interrupts D Fully Programmable Serial Interface Characteristics: − 5-, 6-, 7-, or 8-Bit Characters − Even-, Odd-, or No-Parity Bit − 1-, 1 1/2-, or 2-Stop Bit Generation − Baud Generation (DC to 1-Mbit Per Second) D False Start Bit Detection D Complete Status Reporting Capabilities D Line Break Generation and Detection D Internal Diagnostic Capabilities: − Loopback Controls for Communications Link Fault Isolation − Break, Parity, Overrun, Framing Error Simulation D Fully Prioritized Interrupt System Controls D Modem Control Functions (CTS, RTS, DSR, DTR, RI, and DCD) D 3-State Outputs Provide TTL Drive Capabilities for Bidirectional Data Bus ...