TM8SK64JPU

TM8SK64JPU 8ā388ā608 BY 64ĆBIT SYNCHRONOUS DYNAMIC RAM MODULE Ċ SODIMM D Organization: − TM8SK64JPU . . . 8 388 608 x 64 Bits D Single 3.3-V Power Supply (±10% Tolerance) D Designed for 66-MHz 4-Clock Systems D JEDEC 144-Pin Small Outline Dual-In-Line Memory Module (SODIMM) Without Buffer for Use With Socket D Uses Eight 64M-Bit Synchronous Dynamic RAMs (SDRAMs) (8M × 8-Bit) in Plastic Thin Small-Outline Packages (TSOPs) D Byte-Read/Write Capability D Performance Ranges: D High-Speed, Low-Noise Low-Voltage TTL (LVTTL) Interface SMMS690B − AUGUST 1997 − REVISED FEBRUARY 1998 D Read Latencies 2 and 3 Supported D Support Burst-Interleave and Burst-Interrupt Operations D Burst Length Programmable to 1, 2, 4, and 8 D Four Banks for On-Chip Interleaving (Gapless Access) D Ambient Temperature Range 0°C to 70°C D Gold-Plated Contacts D Pipeline Architecture D Serial Presence Detect (SPD) Using EEPROM ’8SK64JPU-10 SYNCHRONOUS CLOCK CYCLE TIME tCK3 tCK2 10 ns 15 ns ACCESS TIME CLOCK TO OUTPUT tAC3 tAC2 8 ns 9 ns REFRESH INTERVAL tREF 64 ms description The TM8SK64JPU is a 64M-byte, 144-pin SODIMM. The SODIMM is composed of eight TMS664814DGE, 8 388 608 x 8-bit SDRAMs, each in a 400-mil, 54-pin plastic thin small-outline package (TSOP) mounted on a substrate with decoupling capacitors. See the TMS664814 data sheet (literature number SMOS690). operation The TM8SK64JPU operates as eight TMS664814DGE devices that are connected as shown in the TM8SK64JPU functional block diagra...