TMS29F002RT

D Single Power Supply Supports 5-V "10% Read/Write Operation D Organization : . . . 262 144 by 8 Bits D Array-Blocking Architecture − One 16K-Byte Boot Sector − Two 8K-Byte Parameter Sectors − One 32K-Byte Sector − Three 64K-Byte Sectors − Any Combination of Sectors Can Be Erased. Support Full-Chip Erase − Any Combination of Sectors Can Be Marked as Read-Only D Boot-Code Sector Architecture − T = Top Sector − B = Bottom Sector D Sector Protection − Hardware Protection Method That Disables Any Combination of Sectors From Write or Erase Operations Using Standard Programming Equipment D Embedded Program/Erase Algorithms − Automatically Pre-Programs and Erases Any Sector − Automatically Programs and Verifies the Program Data at Specified Address D JEDEC Standards − Compatible With JEDEC Byte Pinouts − Compatible With JEDEC EEPROM Command Set D Fully Automated On-Chip Erase and Program Operations D 100 000 Program/Erase Cycles D Low Power Dissipation D Low Current Consumption − 25-mA Typical Active Read − 30-mA Typical Program/Erase Current − Less Than 100-µA Standby Current D All Inputs/Outputs TTL-Compatible D Erase Suspend/Resume − Supports Reading Data From, or Programming Data to, a Sector Not Being Erased D Hardware-Reset Pin Initializes the Internal-State Machine to the Read Operation TMS29F002RT, TMS29F002RB 262ā144 BY 8ĆBIT FLASH MEMORIES SMJS849B − MARCH 1997 − REVISED JUNE 1998 FM PACKAGE 32-PIN PLCC (TOP VIEW) A12 A15 A16 RESET VCC WE A17 4 3 2 1 32 31 30 A7 A6 A5 ...