ADVANCE INFORMATION
TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS
80-ns Instruction Cycle Time 544 Words of O...
ADVANCE INFORMATION
TMS320 SECOND GENERATION DIGITAL SIGNAL PROCESSORS
80-ns Instruction Cycle Time 544 Words of On-Chip Data RAM 4K Words of On-Chip Secure Program
EPROM (TMS320E25)
4K Words of On-Chip Program ROM
(TMS320C25)
128K Words of Data/Program Space 32-Bit ALU/Accumulator 16 16-Bit Multiplier With a 32-Bit Product Block Moves for Data/Program
Management
Repeat Instructions for Efficient Use of
Program Space
Serial Port for Direct Codec Interface Synchronization Input for Synchronous
Multiprocessor Configurations
Wait States for Communication to Slow
Off-Chip Memories/Peripherals
On-Chip Timer for Control Operations Single 5-V Supply Packaging: 68-Pin PGA, PLCC, and
CER-QUAD
68-to-28 Pin Conversion Adapter Socket for
EPROM Programming
Commercial and Military Versions Available NMOS Technology:
— TMS32020 . . . . . . . . . 200-ns cycle time
CMOS Technology:
— TMS320C25 . . . . . . . . 100-ns cycle time — TMS320E25 . . . . . . . . 100-ns cycle time — TMS320C25-50 . . . . . . 80-ns cycle time
VSS A1 A2 A3 A4 A5 A6 A7
V CC A8 A9
A10 A11 A12 A13 A14 A15
SPRS010B — MAY 1987 — REVISED NOVEMBER 1990
68-Pin GB Package† (Top View)
1 2 3 4 5 6 7 8 9 10 11
A B C D E F G H J K L
68-Pin FN and FZ Packages† (Top View)
D8 D9 D10 D11 D12 D13 D14 D15 READY CLKR CLKX VCC VCC
VSS D7 D6 D5 D4 D3 D2 D1 D0 SYNC INT0 INT1 INT2 VCC DR FSR A0
9 8 7 6 5 4 3 2 1 68 67 66 65 64 63 62 61
10
60
11
59
12
58
13
57
14
56
15
55
16
54
17
53...
