TMS320C44

D Highest Performance Floating-Point Digital Signal Processor (DSP) − TMS320C44-60: 33-ns Instruction Cycle Time, 330 MOPS, 60 MFLOPS, 30 MIPS, 336M Bytes/s − TMS320C44-50: 40-ns Instruction Cycle Time D Four Communication Ports D Six-Channel Direct Memory Address (DMA) Coprocessor D Single-Cycle Conversion to and From IEEE-754 Floating-Point Format D Single Cycle, 1/x, 1/√x D Source-Code Compatible With C3x and C4x D Single-Cycle 40-Bit Floating-Point, 32-Bit Integer Multipliers D Twelve 40-Bit Registers, Eight Auxiliary Registers, 14 Control Registers, and Two Timers D IEEE-1149.1† (JTAG) Boundary-Scan Compatible D Two Identical External Data and Address Buses Supporting Shared Memory Systems and High Data-Rate, Single-Cycle Transfers − High Port-Data Rate of 120M Bytes/s (TMS320C44-60) (Each Bus) − 128M-Byte Program/Data/Peripheral Address Space − Memory-Access Request for Fast, Intelligent Bus Arbitration − Separate Address-Bus, Data-Bus, and Control-Enable Pins − Four Sets of Memory-Control Signals Support Different Speed Memories in Hardware TMS320C44 DIGITAL SIGNAL PROCESSOR SPRS031C − AUGUST 1994 − REVISED MARCH 2004 D Fabricated Using 0.72-µm Enhanced Performance Implanted CMOS (EPIC) Technology by Texas Instruments (TI) D Separate Internal Program-, Data-, and DMA-Coprocessor Buses for Support of Massive Concurrent I/O of Program and Data, Thereby Maximizing Sustained CPU Performance D IDLE2 Clock-Stop Power-Down Mode D Communication-Port-Direction Pin D On-Chip ...