TMS320C6205

D High-Performance Fixed-Point Digital Signal Processor (DSP) − TMS320C6205 − 5-ns Instruction Cycle Time − 200-MHz Clock Rate − Eight 32-Bit Instructions/Cycle − 1600 MIPS D VelociTI Advanced-Very-Long-Instruction- Word (VLIW) TMS320C62x DSP Core − Eight Highly Independent Functional Units: − Six ALUs (32-/40-Bit) − Two 16-Bit Multipliers (32-Bit Result) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional D Instruction Set Features − Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation − Bit-Field Extract, Set, Clear − Bit-Counting − Normalization D 1M-Bit On-Chip SRAM − 512K-Bit Internal Program/Cache (16K 32-Bit Instructions) − 512K-Bit Dual-Access Internal Data (64K Bytes) − Organized as Two 32K-Byte Blocks for Improved Concurrency D 32-Bit External Memory Interface (EMIF) − Glueless Interface to Synchronous Memories: SDRAM or SBSRAM − Glueless Interface to Asynchronous Memories: SRAM and EPROM − 52M-Byte Addressable External Memory Space D Four-Channel Bootloading Direct-Memory-Access (DMA) Controller With an Auxiliary Channel D Flexible Phase-Locked-Loop (PLL) Clock Generator TMS320C6205 FIXEDĆPOINT DIGITAL SIGNAL PROCESSOR SPRS106G − OCTOBER 1999 − REVISED JULY 2006 D 32-Bit/33-MHz Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms to: PCI Specification 2.2 Power Management Interface 1.1 Meets Requirements of PC99 − PCI Access to All...