TMS320C6713

TMS320C6713, TMS320C6713B FLOATING-POINT DIGITAL SIGNAL PROCESSORS SPRS186I − DECEMBER 2001 − REVISED MAY 2004 D Highest-Performance Floating-Point Digital Signal Processors (DSPs): C6713/C6713B − Eight 32-Bit Instructions/Cycle − 32/64-Bit Data Word − 300-, 225-, 200-MHz (GDP), and 200-, 167-MHz (PYP) Clock Rates − 3.3-, 4.4-, 5-, 6-Instruction Cycle Times − 2400/1800, 1800 /1350 , 1600 /1200 , and 1336 /1000 MIPS /MFLOPS − Rich Peripheral Set, Optimized for Audio − Highly Optimized C/C++ Compiler D Advanced Very Long Instruction Word (VLIW) TMS320C67x DSP Core − Eight Independent Functional Units: − Two ALUs (Fixed-Point) − Four ALUs (Floating- and Fixed-Point) − Two Multipliers (Floating- and Fixed-Point) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional D Instruction Set Features − Native Instructions for IEEE 754 − Single- and Double-Precision − Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization D L1/L2 Memory Architecture − 4K-Byte L1P Program Cache (Direct-Mapped) − 4K-Byte L1D Data Cache (2-Way) − 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM D Device Configuration − Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot − Endianness: Little Endian, Big Endian D 32-Bit External Memory Interface (EMIF) − Glueless Interface to SRAM, EPROM, Flash, SB...