TMS320C6713B

TMS320C6713B FLOATINGĆPOINT DIGITAL SIGNAL PROCESSOR D Highest-Performance Floating-Point Digital Signal Processor (DSP): TMS320C6713B − Eight 32-Bit Instructions/Cycle − 32/64-Bit Data Word − 300-, 225-, 200-MHz (GDP and ZDP), and 225-, 200-, 167-MHz (PYP) Clock Rates − 3.3-, 4.4-, 5-, 6-Instruction Cycle Times − 2400/1800, 1800/1350, 1600/1200, and 1336/1000 MIPS/MFLOPS − Rich Peripheral Set, Optimized for Audio − Highly Optimized C/C++ Compiler − Extended Temperature Devices Available D Advanced Very Long Instruction Word (VLIW) TMS320C67x DSP Core − Eight Independent Functional Units: − 2 ALUs (Fixed-Point) − 4 ALUs (Floating-/Fixed-Point) − 2 Multipliers (Floating-/Fixed-Point) − Load-Store Architecture With 32 32-Bit General-Purpose Registers − Instruction Packing Reduces Code Size − All Instructions Conditional D Instruction Set Features − Native Instructions for IEEE 754 − Single- and Double-Precision − Byte-Addressable (8-, 16-, 32-Bit Data) − 8-Bit Overflow Protection − Saturation; Bit-Field Extract, Set, Clear; Bit-Counting; Normalization D L1/L2 Memory Architecture − 4K-Byte L1P Program Cache (Direct-Mapped) − 4K-Byte L1D Data Cache (2-Way) − 256K-Byte L2 Memory Total: 64K-Byte L2 Unified Cache/Mapped RAM, and 192K-Byte Additional L2 Mapped RAM D Device Configuration − Boot Mode: HPI, 8-, 16-, 32-Bit ROM Boot − Endianness: Little Endian, Big Endian D 32-Bit External Memory Interface (EMIF) − Glueless Interface to SRAM, EPROM, Flash, SBSRAM, and SDRAM − 512M-Byte...