Video/Imaging Fixed-Point Digital-Signal Processor
TMS320DM642
www.ti.com
SPRS200N – JULY 2002 – REVISED OCTOBER 2010
TMS320DM642 Video/Imaging Fixed-Point Digital Signa...
Description
TMS320DM642
www.ti.com
SPRS200N – JULY 2002 – REVISED OCTOBER 2010
TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor
Check for Samples: TMS320DM642
1 TMS320DM642 Video/Imaging Fixed-Point Digital Signal Processor
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High-Performance Digital Media Processor – 2-, 1.67-, 1.39-ns Instruction Cycle Time – 500-, 600-, 720-MHz Clock Rate – Eight 32-Bit Instructions/Cycle – 4000, 4800, 5760 MIPS – Fully Software-Compatible With C64x™
VelociTI.2™ Extensions to VelociTI™ Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x™ DSP Core – Eight Highly Independent Functional Units With VelociTI.2™ Extensions:
– 1024M-Byte Total Addressable External Memory Space
Enhanced Direct-Memory-Access (EDMA) Controller (64 Independent Channels)
10/100 Mb/s Ethernet MAC (EMAC) – IEEE 802.3 Compliant – Media Independent Interface (MII) – 8 Independent Transmit (TX) Channels and 1 Receive (RX) Channel
Management Data Input/Output (MDIO) Three Configurable Video Ports
Six ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, or Quad 8-Bit
– Providing a Glueless I/F to Common Video Decoder and Encoder Devices
Arithmetic per Clock Cycle
– Supports Multiple Resolutions/Video Stds
Two Multipliers Support Four 16 x 16-Bit
VCXO Interpolated Control Port (VIC)
Multiplies (32-Bit Results) per Clock Cycle or Eight 8 x 8-Bit Multiplies (16-Bit Results) per Clock Cycle – Load-Store Architecture With Non-Aligned Support – 64 32-Bit General-Purpose Registers – Instr...
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