TMS320F28064

Product Folder Order Now Technical Documents Tools & Software Support & Community TMS320F28069, TMS320F28068, TMS320F28067, TMS320F28066 TMS320F28065, TMS320F28064, TMS320F28063, TMS320F28062 SPRS698G – NOVEMBER 2010 – REVISED MAY 2018 TMS320F2806x Piccolo™ Microcontrollers 1 Device Overview 1.1 Features 1 High-Efficiency 32-Bit CPU (TMS320C28x) – 90 MHz (11.11-ns Cycle Time) – 16 × 16 and 32 × 32 Multiply and Accumulate (MAC) Operations – 16 × 16 Dual MAC – Harvard Bus Architecture – Atomic Operations – Fast Interrupt Response and Processing – Unified Memory Programming Model – Code-Efficient (in C/C++ and Assembly) Floating-Point Unit (FPU) – Native Single-Precision Floating-Point Operations Programmable Control Law Accelerator (CLA) – 32-Bit Floating-Point Math Accelerator – Executes Code Independently of the Main CPU Viterbi, Complex Math, CRC Unit (VCU) – Extends C28x Instruction Set to Support Complex Multiply, Viterbi Operations, and Cyclic Redundency Check (CRC) Embedded Memory – Up to 256KB of Flash – Up to 100KB of RAM – 2KB of One-Time Programmable (OTP) ROM 6-Channel Direct Memory Access (DMA) Low Device and System Cost – Single 3.3-V Supply – No Power Sequencing Requirement – Integrated Power-on Reset and Brownout Reset – Low-Power Operating Modes – No Analog Support Pin Endianness: Little Endian JTAG Boundary Scan Support – IEEE Standard 1149.1-1990 Standard Test Access Port and Boundary Scan Architecture Clocking – Two Internal Zero-P...