Floating-Point Digital Signal Processor
TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS
D Advanced Multibus Architecture With Three
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Description
TMS320C54x, TMS320LC54x, TMS320VC54x FIXED-POINT DIGITAL SIGNAL PROCESSORS
D Advanced Multibus Architecture With Three
Separate 16-Bit Data Memory Buses and One Program Memory Bus
D 40-Bit Arithmetic Logic Unit (ALU)
Including a 40-Bit Barrel Shifter and Two Independent 40-Bit Accumulators
D 17- × 17-Bit Parallel Multiplier Coupled to a
40-Bit Dedicated Adder for Non-Pipelined Single-Cycle Multiply/Accumulate (MAC) Operation
D Compare, Select, and Store Unit (CSSU) for
the Add/Compare Selection of the Viterbi Operator
D Exponent Encoder to Compute an
Exponent Value of a 40-Bit Accumulator Value in a Single Cycle
D Two Address Generators With Eight
Auxiliary Registers and Two Auxiliary Register Arithmetic Units (ARAUs)
D Data Bus With a Bus Holder Feature D Address Bus With a Bus Holder Feature
(’548 and ’549 Only)
D Extended Addressing Mode for 8M × 16-Bit
Maximum Addressable External Program Space (’548 and ’549 Only)
D 192K × 16-Bit Maximum Addressable
Memory Space (64K Words Program, 64K Words Data, and 64K Words I/O)
D On-Chip ROM with Some Configurable to
Program/Data Memory
D Dual-Access On-Chip RAM D Single-Access On-Chip RAM (’548/’549) D Single-Instruction Repeat and
Block-Repeat Operations for Program Code
D Block-Memory-Move Instructions for Better
Program and Data Management
D Instructions With a 32-Bit Long Word
Operand
D Instructions With Two- or Three-Operand
Reads
D Arithmetic Instructions With Parallel Store
and Parallel Load
D Conditional Store Instructions...
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