TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC ...
TMS664414, TMS664814, TMS664164
4 194 304 BY 4-BIT/2 097 152 BY 8-BIT/1 048 576 BY 16-BIT BY 4-BANK
SYNCHRONOUS DYNAMIC RANDOM-ACCESS MEMORIES
SMOS695A – APRIL 1998 – REVISED JULY 1998
D Organization . . .
1 048 576 x 16 Bits x 4 Banks
2 097 152 x 8 Bits x 4 Banks
4 194 304 x 4 Bits x 4 Banks
D 3.3-V Power Supply (± 10% Tolerance) D Four Banks for On-Chip Interleaving for
x8/x16 (Gapless Access) Depending on
Organizations
D High Bandwidth – Up to 125-MHz Data
Rates
D Burst Length Programmable to 1, 2, 4, 8 D Programmable Output Sequence – Serial or
Interleave
D Chip-Select and Clock-Enable for
Enhanced-System Interfacing
D Cycle-by-Cycle DQ Bus Mask Capability D Only x16 SDRAM Configuration Supports
Upper-/Lower-Byte Masking Control
D Programmable CAS Latency From Column
Address
D Performance Ranges:
D Pipeline Architecture (Single-Cycle
Architecture)
D Single Write/Read Burst D Self-Refresh Capability (Every 16 ms) D Low-Noise, Low-
Voltage
Transistor-Transistor Logic (LVTTL)
Interface
D Power-Down Mode D Compatible With JEDEC Standards D 16K RAS-Only Refresh (Total for All Banks) D 4K Auto Refresh (Total for All Banks)/64 ms D Automatic Precharge and Controlled
Precharge
D Burst Interruptions Supported:
– Read Interruption
– Write Interruption
– Precharge Interruption
D Support Clock-Suspend Operation (Hold
Command)
D Intel PC100 Compliant (-8 and -8A parts)
’664xx4-8 ’664xx4-8A ’664xx4-10
SYNCHRONOUS CLOCK CYLE TIME
tCK3 8 ns
tCK2 10 ns
8 ns 15 ns
10 ns
15 ns
ACCE...
