TN2524

TN2524 N-Channel Enhancement-Mode Vertical DMOS FET Features 2V Maximum Low Threshold High Input Impedance 125 pF Maximum Low Input Capacitance Fast Switching Speeds Low On-Resistance Free from Secondary Breakdown Low Input and Output Leakage Applications Logic-Level Interfaces (Ideal for TTL and CMOS) Solid-State Relays Battery-Operated Systems Photovoltaic Drives Analog Switches General Purpose Line Drivers Telecommunication Switches General Description The TN2524 low-threshold Enhancement-mode (normally-off) transistor uses a vertical DMOS structure and a well-proven silicon-gate manufacturing process. This combination produces a device with the power handling capabilities of bipolar transistors and the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, this device is free from thermal runaway and thermally induced secondary breakdown. Microchip’s vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where very low threshold voltage, high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired. Package Type See Table 3-1 for pin information. 3-lead SOT-89 (Top view) DRAIN SOURCE DRAIN GATE  2020 Microchip Technology Inc. DS20005952A-page 1 TN2524 1.0 ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings† Drain-to-Source Voltage ...........................................................