TPIC1501A

TPIC1501A QUAD AND HEX POWER DMOS ARRAY SLIS046A – MAY 1995 – REVISED JUNE 1996 D Low rDS(on): 0.1 Ω Typ (Full H-Bridge) 0.4 Ω Typ (Triple Half H-Bridge) D Pulsed Current: 12 A Per Channel (Full H-Bridge) 6 A Per Channel (Triple Half H-Bridge) D Matched Sense Transistor for Class A-B Linear Operation D Fast Commutation Speed description The TPIC1501A is a monolithic power array that consists of ten electrically isolated N-channel enhancement-mode power DMOS transistors, four of which are configured as a full H-bridge and six as a triple half H-bridge. The lower stage of the full H-bridge features an integrated sense FET to allow biasing of the bridge in class A-B operation. DW PACKAGE (TOP VIEW) OUTPUT3 GND GATE3B GATE2B SENSE OUTPUT2 GATE4B GATE2A GATE5B VDD2 OUTPUT4 SOURCE 1 2 3 4 5 6 7 8 9 10 11 12 24 VDD3 23 GND 22 GATE3A 21 GATE1B 20 GATE2C 19 OUTPUT1 18 GATE4A 17 GATE1A 16 GATE5A 15 VDD1 14 VDD3 13 OUTPUT5 The TPIC1501A is offered in a 24-pin wide-body surface-mount (DW) package and is characterized for operation over the case temperature range of – 40°C to 125°C. schematic VDD1 15 VDD2 10 VDD3 14, 24 Q1A 17 GATE1A 19 OUTPUT1 Q1B 21 GATE1B D1 SENSE 5 Q2C 20 GATE2C Q2A 8 Q3A 22 Q4A 18 GATE2A GATE3A GATE4A 61 11 D2 OUTPUT2 OUTPUT3 D3 OUTPUT4 Q2B 4 GATE2B Q3B 3 GATE3B Q4B 7 GATE4B 12 SOURCE Q5A 16 GATE5A 13 OUTPUT5 Q5B 9 GATE5B 2, 23 GND NOTES: A. Pins 2 and 23 must be externally connected. B. Pins 14 and 24 must be externally connected. C. No...