TPS53317A

Product Folder Sample & Buy Technical Documents Tools & Software Support & Community TPS53317A SLUSC63A – NOVEMBER 2015 – REVISED DECEMBER 2015 TPS53317A 6-A Output, D-CAP+ Mode, Synchronous Step-Down, Integrated-FET Converter for DDR Memory Termination 1 Features 1 TI-Proprietary Integrated MOSFET and Packaging Technology Supports DDR Memory Termination with up to 6-A Continuous Output Source or Sink Current External Tracking Minimum External Components Count 0.9-V to 6-V Conversion Voltage D-CAP+™ Mode Architecture Supports All MLCC Output Capacitors and SP/POSCAP Selectable SKIP Mode or Forced CCM Optimized Efficiency at Light and Heavy Loads Selectable 600-kHz or 1-MHz Switching Frequency Selectable Overcurrent Limit (OCL) Overvoltage, Over-Temperature and Hiccup Undervoltage Protection Adjustable Output Voltage from 0.45 V to 2 V 3.5 mm × 4 mm, 20-Pin, VQFN Package 2 Applications Memory Termination Regulator for DDR, DDR2, DDR3, DDR3L, and DDR4 VTT Termination Low-Voltage Applications for 0.9-V to 6-V Input Rails 3 Description The TPS53317A device is a FET-integrated synchronous buck regulator designed mainly for DDR termination. It can provide a regulated output at ½ VDDQ with both sink and source capability. The TPS53317A device employs D-CAP+ mode operation that provides ease of use, low external component count and fast transient response. The device can also be used for other point-of-load (POL) regulation applications requiri...