AMPLIFIER. UA740 Datasheet

UA740 Datasheet PDF


Part UA740
Description FET INPUT OPERATIONAL AMPLIFIER
Feature p-A740 FET INPUT OPERATIONAL AMPLIFIER FAIRCHILD LINEAR INTEGRATED CIRCUITS GENERAL DESCRIPTION - T.
Manufacture Fairchild
Datasheet
Download UA740 Datasheet


p-A740 FET INPUT OPERATIONAL AMPLIFIER FAIRCHILD LINEAR INTE UA740 Datasheet




UA740
p-A740
FET INPUT OPERATIONAL AMPLIFIER
FAIRCHILD LINEAR INTEGRATED CIRCUITS
GENERAL DESCRIPTION - The jLA740 is a high performance monolithic FET Input Operational
Amplifier constructed using the Fairchild Planar* epitaxial process. It is intended for a wide range of
analog applications where very high input impedance ;s required and features very low input offset
current and very low input bias current. High slew rate, high common mode voltage range and
absence of latch-up make the jLA740 ideal for use as a voltage follower. The high gain and wide
range of operating voltages provide superior performance in active filters, integrators, summing
amplifiers, sample-and-hold circuits, transducer amplifiers, and other general feedback applications.
The jLA740 is short circuit protected and has the same pin configuration as the popular jLA741
operational amplifier. No external components for frequency compensation are required as the internal
6 dB/octave roll-off insures stability in closed loop applications.
• HIGH INPUT IMPEDANCE .•• 1,000,000 Mrl
• NO FREQUENCY COMPENSATION REQUIRED
• SHORT-CIRCUIT PROTECTION
• OFFSET VOLTAGE NULL CAPABILITY
• LARGE COMMON-MODE AND DIFFERENTIAL VOLTAGE RANGES
• NO LATCH UP
ABSOLUTE MAXIMUM RATINGS
Supply Voltage
Internal Power Dissipation (Note 1)
Differential Input Voltage
I nput Voltage (Note 2)
Voltage between Offset Null and V+
Storage Temperature Range
Operating Temperature Range
Military (jLA740)
Commercial (jLA740C)
Lead Temperature (Soldering, 60 seconds)
Output Short-Circuit Duration (Note 3)
±22V
500mW
±30V
±15V
±o.5V
-65°C to +150oC
-55°C to +1250 C
OOC to +70oC
300°C
Indefinite
CONNECTION DIAGRAM
B-LEADMETAL CAN
(TOP VIEW)
PACKAGE OUTLINE 5S
PACKAGE CODE H
NC
NU I E: hn 4. ~onnec"Cea 'to Case.
ORDER INFORMATION
TYPE
PART NO.
jLA740
jLA740HM
jLA740C
jLA740HC
OFFSET
NULL
l-~--t:=- a"
OUTPUT
Notes on following pages.
5-109
·Planar is a patented Fairchild process.



UA740
FAIRCHILD • p.A740
JlA740
ELECTRICAL CHARACTERISTICS (VS = ±15V, T C = 250 C unless otherwise specified)
PARAMETER
CONDITIONS
I nput Offset Voltage
Input Offset Current [Note 4]
Input Current (either input) [Note 4]
Input Resistance
Large Signal Voltage Gain
Output Resistance
Output Short Circuit Current
Common Mode Rejection Ratio
Supply Voltage Rejection Ratio
Supply Current
Power Consumption
Slew Rate
Unity Gain Bandwidth
RS .s;;; 100 kn
RL ;;;'2kn, VOUT = ±10V
ITransient Response Rise Time
(Unity Gain)
I Overshoot
CL .s;;;100pF, RL = 2kn, VIN = 100mV
The following specifications apply for TC = -55°C to +85"C:
Input Voltage Range
Large Signal Voltage Gain
RL;;' 2 kn, VOUT = ±10 V
Output Voltage Swing
RL ;;;'10kn
RL;;;' 2kn
Input Offset Voltage
RS.s;;; 100kn
Input Offset Current
TA =-55OC
TA =+85O C
Input Current (either input)
T A = - 5 5O C
TA = +85OC
MIN
50,000
64
±1O
25,000
±12
±10
TYP
10
40
100
1,000,000
1,000,000
75
20
80
70
4.2
126
6.0
3.0
110
10
±14
±13
15
30
185
2.5
MAX
20
150
200
300
5.2
156
UNITS
mV
pA
pA
Mn
V/V
n
mA
dB
!-'V/V
mA
mW
V/!-'s
MHz
ns
20 %
±12
30
200
4.0
V
V/V
V
V
mV
pA
pA
pA
nA
VOLTAGE OFFSET
NULL CIRCUIT
r+
K 2 5
V3 +
TRANSIENT RESPONSE
TEST CIRCUIT
:».
OVIN
-=-
t VOUT
Rl .
~
-=-
5-110






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